From e0aba04da0323efc079ce0a2b78139c4d0d49fa5 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 13 Mar 2009 13:37:35 -0700
Subject: [PATCH] Add DCC register dumping.

---
 src/i810_reg.h   |  1 +
 src/i830_debug.c | 28 ++++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/src/i810_reg.h b/src/i810_reg.h
index 3114b42c..bc462fae 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -114,6 +114,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define BITBLT_STATUS          0x01
 
 #define CHDECMISC	0x10111
+#define DCC			0x10200
 #define C0DRB0			0x10200
 #define C0DRB1			0x10202
 #define C0DRB2			0x10204
diff --git a/src/i830_debug.c b/src/i830_debug.c
index 4693cf9c..86f5f21d 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -53,6 +53,33 @@ DEBUGSTRING(i830_16bit_func)
     return XNFprintf("0x%04x", (uint16_t)val);
 }
 
+DEBUGSTRING(i830_debug_dcc)
+{
+    char *addressing = NULL;
+
+    if (!IS_MOBILE(pI830))
+	return NULL;
+
+    if (IS_I965G(pI830)) {
+	if (val & (1 << 1))
+	    addressing = "dual channel interleaved";
+	else
+	    addressing = "single or dual channel asymmetric";
+    } else {
+	switch (val & 3) {
+	case 0: addressing = "single channel"; break;
+	case 1: addressing = "dual channel asymmetric"; break;
+	case 2: addressing = "dual channel interleaved"; break;
+	case 3: addressing = "unknown channel layout"; break;
+	}
+    }
+
+    return XNFprintf("%s, XOR randomization: %sabled, XOR bit: %d",
+		     addressing,
+		     (val & (1 << 10)) ? "dis" : "en",
+		     (val & (1 << 9)) ? 17 : 11);
+}
+
 DEBUGSTRING(i830_debug_chdecmisc)
 {
     char *enhmodesel = NULL;
@@ -559,6 +586,7 @@ static struct i830SnapshotRec {
     char *(*debug_output)(I830Ptr pI830, int reg, uint32_t val);
     uint32_t val;
 } i830_snapshot[] = {
+    DEFINEREG2(DCC, i830_debug_dcc),
     DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
     DEFINEREG_16BIT(C0DRB0),
     DEFINEREG_16BIT(C0DRB1),