Aurelien
/
xf86-video-intel
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add some caution with PCI write posting and DPLL delays to i830_crtc_dpms. 

While it doesn't specifically help/hurt my test case, we've seen enough
mysterious behavior that caution is probably warranted.
This commit is contained in:
Eric Anholt 2006-12-13 00:26:27 -08:00
parent df0a5a25aa
commit e27372e85a
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/i830_display.c
View File

@ -507,6 +507,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Enable the DPLL */
temp = INREG(dpll_reg);
OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
(void)INREG(dpll_reg); /* write posting */
/* Wait for the clocks to stabilize. */
usleep(150);
@ -538,6 +539,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Flush the plane changes */
OUTREG(dspbase_reg, INREG(dspbase_reg));
(void)INREG(dspbase_reg); /* write posting */
if (!IS_I9XX(pI830)) {
/* Wait for vblank for the disable to take effect */
@ -547,12 +549,17 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Next, disable display pipes */
temp = INREG(pipeconf_reg);
OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
(void)INREG(pipeconf_reg); /* write posting */
/* Wait for vblank for the disable to take effect. */
i830WaitForVblank(pScrn);
temp = INREG(dpll_reg);
OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
(void)INREG(dpll_reg); /* write posting */
/* Wait for the clocks to turn off. */
usleep(150);
break;
}
}