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unifdef LIBPCIACCESS and XSERVER_LIBPCIACCESS. 

Depending on new server means these are always present.
This commit is contained in:
Eric Anholt 2009-04-21 15:49:01 -07:00
parent 4653a7db62
commit e5133a94dc
18 changed files with 13 additions and 462 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
configure.ac
View File

@ -117,21 +117,7 @@ if test x$DRI = xauto; then
fi
AC_MSG_RESULT([$DRI])
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
CFLAGS="$save_CFLAGS"
if test x$XSERVER_LIBPCIACCESS = xyes; then
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10])
else
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10],
have_libpciaccess=yes,
have_libpciaccess=no)
fi
AM_CONDITIONAL(XSERVER_LIBPCIACCESS, test "x$XSERVER_LIBPCIACCESS" = xyes)
AM_CONDITIONAL(LIBPCIACCESS,
test "x$XSERVER_LIBPCIACCESS" = xyes -o "x$have_libpciaccess" = xyes)
PKG_CHECK_MODULES([PCIACCESS], [pciaccess >= 0.10])
SAVE_CPPFLAGS="$CPPFLAGS"
CPPFLAGS="$CPPFLAGS $XORG_CFLAGS"

8
src/Makefile.am
View File

@ -18,11 +18,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
if LIBPCIACCESS
REGDUMPER = reg_dumper
endif
SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 $(REGDUMPER)
SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper
# this is obnoxious:
# -module lets us name the module exactly how we want
@ -37,9 +33,7 @@ intel_drv_la_LTLIBRARIES = intel_drv.la
intel_drv_la_LDFLAGS = -module -avoid-version
intel_drv_ladir = @moduledir@/drivers
intel_drv_la_LIBADD = -lm @DRM_LIBS@ -ldrm_intel ../uxa/libuxa.la
if XSERVER_LIBPCIACCESS
intel_drv_la_LIBADD += @PCIACCESS_LIBS@
endif
INTEL_DRI_SRCS = \
i810_dri.c \

3
src/bios_reader/Makefile.am
View File

@ -3,7 +3,6 @@ AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @PCIACCESS_CFLAGS@ \
noinst_PROGRAMS = bios_reader $(BIOS_DUMPER) $(SWF_DUMPER)
if LIBPCIACCESS
BIOS_DUMPER = bios_dumper
bios_dumper_SOURCES = bios_dumper.c
@ -15,5 +14,3 @@ SWF_DUMPER = swf_dumper
swf_dumper_SOURCES = swf_dumper.c
swf_dumper_LDADD = $(PCIACCESS_LIBS)
endif

13
src/common.h
View File

@ -322,21 +322,12 @@ extern int I810_DEBUG;
#define PCI_CHIP_G41_G_BRIDGE 0x2E30
#endif
#if XSERVER_LIBPCIACCESS
#define I810_MEMBASE(p,n) (p)->regions[(n)].base_addr
#define VENDOR_ID(p) (p)->vendor_id
#define DEVICE_ID(p) (p)->device_id
#define SUBVENDOR_ID(p) (p)->subvendor_id
#define SUBSYS_ID(p) (p)->subdevice_id
#define CHIP_REVISION(p) (p)->revision
#else
#define I810_MEMBASE(p,n) (p)->memBase[n]
#define VENDOR_ID(p) (p)->vendor
#define DEVICE_ID(p) (p)->chipType
#define SUBVENDOR_ID(p) (p)->subsysVendor
#define SUBSYS_ID(p) (p)->subsysCard
#define CHIP_REVISION(p) (p)->chipRev
#endif
#define IS_I810(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810 || \
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I810_DC100 || \
@ -403,9 +394,7 @@ extern int I810_DEBUG;
#define PIPE_NAME(n) ('A' + (n))
#if XSERVER_LIBPCIACCESS
struct pci_device *
intel_host_bridge (void);
#endif
#endif /* _INTEL_COMMON_H_ */

7
src/i810.h
View File

@ -51,9 +51,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "vgaHW.h"
#include "xorg-server.h"
#ifdef XSERVER_LIBPCIACCESS
#include <pciaccess.h>
#endif
#ifdef XF86DRI
#include "xf86drm.h"
@ -190,12 +188,7 @@ typedef struct _I810Rec {
unsigned long MMIOAddr;
IOADDRESS ioBase;
EntityInfoPtr pEnt;
#if XSERVER_LIBPCIACCESS
struct pci_device *PciInfo;
#else
pciVideoPtr PciInfo;
PCITAG PciTag;
#endif
I810RingBuffer *LpRing;
unsigned int BR[20];

15
src/i810_dri.c
View File

@ -354,14 +354,8 @@ I810DRIScreenInit(ScreenPtr pScreen)
} else {
pDRIInfo->busIdString = xalloc(64);
sprintf(pDRIInfo->busIdString, "PCI:%d:%d:%d",
#if XSERVER_LIBPCIACCESS
((pI810->PciInfo->domain << 8) | pI810->PciInfo->bus),
pI810->PciInfo->dev, pI810->PciInfo->func
#else
((pciConfigPtr) pI810->PciInfo->thisCard)->busnum,
((pciConfigPtr) pI810->PciInfo->thisCard)->devnum,
((pciConfigPtr) pI810->PciInfo->thisCard)->funcnum
#endif
);
}
pDRIInfo->ddxDriverMajorVersion = I810_MAJOR_VERSION;
@ -978,19 +972,10 @@ I810DRIScreenInit(ScreenPtr pScreen)
if (!pI810DRI->irq) {
pI810DRI->irq = drmGetInterruptFromBusID(pI810->drmSubFD,
#if XSERVER_LIBPCIACCESS
((pI810->PciInfo->domain << 8) |
pI810->PciInfo->bus),
pI810->PciInfo->dev,
pI810->PciInfo->func
#else
((pciConfigPtr) pI810->
PciInfo->thisCard)->busnum,
((pciConfigPtr) pI810->
PciInfo->thisCard)->devnum,
((pciConfigPtr) pI810->
PciInfo->thisCard)->funcnum
#endif
);
if ((drmCtlInstHandler(pI810->drmSubFD, pI810DRI->irq)) != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,

245
src/i810_driver.c
View File

@ -95,14 +95,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
static void I810Identify(int flags);
#if XSERVER_LIBPCIACCESS
static Bool intel_pci_probe (DriverPtr drv,
int entity_num,
struct pci_device *dev,
intptr_t match_data);
#else
static Bool I810Probe(DriverPtr drv, int flags);
#endif
#ifndef I830_ONLY
static Bool I810PreInit(ScrnInfoPtr pScrn, int flags);
@ -120,9 +116,6 @@ static ModeStatus I810ValidMode(int scrnIndex, DisplayModePtr mode,
Bool verbose, int flags);
#endif /* I830_ONLY */
#if XSERVER_LIBPCIACCESS
#define INTEL_DEVICE_MATCH(d,i) \
{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0, 0, (i) }
@ -162,25 +155,17 @@ static const struct pci_id_match intel_device_match[] = {
{ 0, 0, 0 },
};
#endif /* XSERVER_LIBPCIACCESS */
_X_EXPORT DriverRec I810 = {
I810_VERSION,
I810_DRIVER_NAME,
I810Identify,
#if XSERVER_LIBPCIACCESS
NULL,
#else
I810Probe,
#endif
I810AvailableOptions,
NULL,
0,
NULL,
#if XSERVER_LIBPCIACCESS
intel_device_match,
intel_pci_probe
#endif
};
/* *INDENT-OFF* */
@ -482,11 +467,7 @@ i810Setup(pointer module, pointer opts, int *errmaj, int *errmin)
if (!setupDone) {
setupDone = 1;
xf86AddDriver(&I810, module,
#if XSERVER_LIBPCIACCESS
HaveDriverFuncs
#else
0
#endif
);
/*
@ -575,7 +556,6 @@ I810AvailableOptions(int chipid, int busid)
#endif
}
#if XSERVER_LIBPCIACCESS
struct pci_device *
intel_host_bridge (void)
{
@ -641,147 +621,6 @@ static Bool intel_pci_probe (DriverPtr driver,
}
return scrn != NULL;
}
#else /* XSERVER_LIBPCIACCESS */
/*
* I810Probe --
*
* Look through the PCI bus to find cards that are I810 boards.
* Setup the dispatch table for the rest of the driver functions.
*
*/
static Bool
I810Probe(DriverPtr drv, int flags)
{
int i, numUsed, numDevSections, *usedChips;
DevUnion *pPriv;
GDevPtr *devSections;
Bool foundScreen = FALSE;
pciVideoPtr *VideoInfo;
pciVideoPtr *ppPci;
PciChipsets *id;
/*
* Find the config file Device sections that match this
* driver, and return if there are none.
*/
if ((numDevSections =
xf86MatchDevice(I810_DRIVER_NAME, &devSections)) <= 0 ) {
return FALSE;
}
/*
* This probing is just checking the PCI data the server already
* collected.
*/
if (!(VideoInfo = xf86GetPciVideoInfo()))
return FALSE;
/*
* Mobile platforms may have both function 0 and 1 active, but they
* are handled as a single entity. To make sure that the function 1
* entity isn't assigned to a screen, check for and claim it here
* first.
*
* XXX If function 1's resources are ever needed, they'll need to be
* added to the screen and marked active.
*/
for (ppPci = VideoInfo; ppPci != NULL && *ppPci != NULL; ppPci++) {
if ((*ppPci)->vendor == PCI_VENDOR_INTEL &&
(*ppPci)->func == 1) {
for (id = I810PciChipsets; id->PCIid != -1; id++) {
if (id->PCIid == (*ppPci)->chipType) {
/* Claim slot */
if (xf86CheckPciSlot((*ppPci)->bus, (*ppPci)->device,
(*ppPci)->func)) {
xf86ClaimPciSlot((*ppPci)->bus, (*ppPci)->device,
(*ppPci)->func, drv, id->PCIid,
NULL, FALSE);
}
break;
}
}
}
}
/* Look for Intel i8xx devices. */
numUsed = xf86MatchPciInstances(I810_NAME, PCI_VENDOR_INTEL,
I810Chipsets, I810PciChipsets,
devSections, numDevSections,
drv, &usedChips);
if (flags & PROBE_DETECT) {
if (numUsed > 0)
foundScreen = TRUE;
} else {
for (i = 0; i < numUsed; i++) {
ScrnInfoPtr pScrn = NULL;
/* Allocate new ScrnInfoRec and claim the slot */
if ((pScrn = xf86ConfigPciEntity(pScrn, 0, usedChips[i],
I810PciChipsets, NULL, NULL, NULL,
NULL, NULL))) {
EntityInfoPtr pEnt;
pEnt = xf86GetEntityInfo(usedChips[i]);
pScrn->driverVersion = I810_VERSION;
pScrn->driverName = I810_DRIVER_NAME;
pScrn->name = I810_NAME;
pScrn->Probe = I810Probe;
foundScreen = TRUE;
switch (pEnt->chipset) {
case PCI_CHIP_845_G:
case PCI_CHIP_I865_G:
case PCI_CHIP_I830_M:
case PCI_CHIP_I855_GM:
case PCI_CHIP_I915_G:
case PCI_CHIP_E7221_G:
case PCI_CHIP_I915_GM:
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I945_GME:
case PCI_CHIP_IGD_GM:
case PCI_CHIP_IGD_G:
case PCI_CHIP_I965_G:
case PCI_CHIP_G35_G:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
case PCI_CHIP_I965_GM:
case PCI_CHIP_I965_GME:
case PCI_CHIP_G33_G:
case PCI_CHIP_Q35_G:
case PCI_CHIP_Q33_G:
case PCI_CHIP_GM45_GM:
case PCI_CHIP_IGD_E_G:
case PCI_CHIP_G45_G:
case PCI_CHIP_Q45_G:
case PCI_CHIP_G41_G:
I830InitpScrn(pScrn);
break;
#ifndef I830_ONLY
default:
pScrn->PreInit = I810PreInit;
pScrn->ScreenInit = I810ScreenInit;
pScrn->SwitchMode = I810SwitchMode;
pScrn->AdjustFrame = I810AdjustFrame;
pScrn->EnterVT = I810EnterVT;
pScrn->LeaveVT = I810LeaveVT;
pScrn->FreeScreen = I810FreeScreen;
pScrn->ValidMode = I810ValidMode;
break;
#endif
}
}
}
}
xfree(usedChips);
xfree(devSections);
return foundScreen;
}
#endif /* else XSERVER_LIBPCIACCESS */
#ifndef I830_ONLY
static void
@ -873,10 +712,6 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
pI810->ioBase = hwp->PIOOffset;
pI810->PciInfo = xf86GetPciInfoForEntity(pI810->pEnt->index);
#if !XSERVER_LIBPCIACCESS
pI810->PciTag = pciTag(pI810->PciInfo->bus, pI810->PciInfo->device,
pI810->PciInfo->func);
#endif
if (xf86RegisterResources(pI810->pEnt->index, NULL, ResNone))
return FALSE;
@ -1015,45 +850,11 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, from, "Chipset: \"%s\"\n",
(pScrn->chipset != NULL) ? pScrn->chipset : "Unknown i810");
#if XSERVER_LIBPCIACCESS
pI810->LinearAddr = pI810->PciInfo->regions[0].base_addr;
#else
if (pI810->pEnt->device->MemBase != 0) {
pI810->LinearAddr = pI810->pEnt->device->MemBase;
from = X_CONFIG;
} else {
if (pI810->PciInfo->memBase[1] != 0) {
pI810->LinearAddr = pI810->PciInfo->memBase[0] & 0xFF000000;
from = X_PROBED;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"No valid FB address in PCI config space\n");
I810FreeRec(pScrn);
return FALSE;
}
}
#endif
xf86DrvMsg(pScrn->scrnIndex, from, "Linear framebuffer at 0x%lX\n",
(unsigned long)pI810->LinearAddr);
#if XSERVER_LIBPCIACCESS
pI810->MMIOAddr = pI810->PciInfo->regions[1].base_addr;
#else
if (pI810->pEnt->device->IOBase != 0) {
pI810->MMIOAddr = pI810->pEnt->device->IOBase;
from = X_CONFIG;
} else {
if (pI810->PciInfo->memBase[1]) {
pI810->MMIOAddr = pI810->PciInfo->memBase[1] & 0xFFF80000;
from = X_PROBED;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"No valid MMIO address in PCI config space\n");
I810FreeRec(pScrn);
return FALSE;
}
}
#endif
xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
(unsigned long)pI810->MMIOAddr);
@ -1072,11 +873,7 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
{
uint32_t whtcfg_pamr_drp;
#if XSERVER_LIBPCIACCESS
pci_device_cfg_read_u32(pI810->PciInfo, & whtcfg_pamr_drp, WHTCFG_PAMR_DRP);
#else
whtcfg_pamr_drp = pciReadLong(pI810->PciTag, WHTCFG_PAMR_DRP);
#endif
/* Need this for choosing watermarks.
*/
@ -1129,18 +926,10 @@ I810PreInit(ScrnInfoPtr pScrn, int flags)
/* Calculate Fixed Offsets depending on graphics aperture size */
{
#if XSERVER_LIBPCIACCESS
struct pci_device *bridge = intel_host_bridge ();
uint32_t smram_miscc;
pci_device_cfg_read_u32 (bridge, & smram_miscc, SMRAM_MISCC);
#else
PCITAG bridge;
long smram_miscc;
bridge = pciTag(0, 0, 0); /* This is always the host bridge */
smram_miscc = pciReadLong(bridge, SMRAM_MISCC);
#endif
if ((smram_miscc & GFX_MEM_WIN_SIZE) == GFX_MEM_WIN_32M) {
pI810->FbMapSize = 0x1000000;
@ -1331,10 +1120,8 @@ I810MapMMIO(ScrnInfoPtr pScrn)
{
int mmioFlags;
I810Ptr pI810 = I810PTR(pScrn);
#if XSERVER_LIBPCIACCESS
struct pci_device *const device = pI810->PciInfo;
int err;
#endif
#if !defined(__alpha__)
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
@ -1342,7 +1129,6 @@ I810MapMMIO(ScrnInfoPtr pScrn)
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT | VIDMEM_SPARSE;
#endif
#if XSERVER_LIBPCIACCESS
err = pci_device_map_range (device,
pI810->MMIOAddr,
I810_REG_SIZE,
@ -1355,13 +1141,6 @@ I810MapMMIO(ScrnInfoPtr pScrn)
strerror (err), err);
return FALSE;
}
#else
pI810->MMIOBase = xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pI810->PciTag,
pI810->MMIOAddr, I810_REG_SIZE);
if (!pI810->MMIOBase)
return FALSE;
#endif
return TRUE;
}
@ -1369,17 +1148,12 @@ static Bool
I810MapMem(ScrnInfoPtr pScrn)
{
I810Ptr pI810 = I810PTR(pScrn);
#if XSERVER_LIBPCIACCESS
struct pci_device *const device = pI810->PciInfo;
int err;
#else
long i;
#endif
if (!I810MapMMIO(pScrn))
return FALSE;
#if XSERVER_LIBPCIACCESS
err = pci_device_map_range (device,
pI810->LinearAddr,
pI810->FbMapSize,
@ -1392,15 +1166,6 @@ I810MapMem(ScrnInfoPtr pScrn)
strerror (err), err);
return FALSE;
}
#else
for (i = 2; i < pI810->FbMapSize; i <<= 1) ;
pI810->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
pI810->PciTag,
pI810->LinearAddr, i);
if (!pI810->FbBase)
return FALSE;
#endif
pI810->LpRing->virtual_start = pI810->FbBase + pI810->LpRing->mem.Start;
@ -1412,12 +1177,7 @@ I810UnmapMMIO(ScrnInfoPtr pScrn)
{
I810Ptr pI810 = I810PTR(pScrn);
#if XSERVER_LIBPCIACCESS
pci_device_unmap_range (pI810->PciInfo, pI810->MMIOBase, I810_REG_SIZE);
#else
xf86UnMapVidMem(pScrn->scrnIndex, (pointer) pI810->MMIOBase,
I810_REG_SIZE);
#endif
pI810->MMIOBase = NULL;
}
@ -1426,12 +1186,7 @@ I810UnmapMem(ScrnInfoPtr pScrn)
{
I810Ptr pI810 = I810PTR(pScrn);
#if XSERVER_LIBPCIACCESS
pci_device_unmap_range (pI810->PciInfo, pI810->FbBase, pI810->FbMapSize);
#else
xf86UnMapVidMem(pScrn->scrnIndex, (pointer) pI810->FbBase,
pI810->FbMapSize);
#endif
pI810->FbBase = NULL;
I810UnmapMMIO(pScrn);
return TRUE;

7
src/i830.h
View File

@ -60,9 +60,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "xf86RandR12.h"
#include "xorg-server.h"
#ifdef XSERVER_LIBPCIACCESS
#include <pciaccess.h>
#endif
#include "xf86drm.h"
#include "sarea.h"
@ -420,12 +418,7 @@ typedef struct _I830Rec {
unsigned long MMIOAddr;
IOADDRESS ioBase;
EntityInfoPtr pEnt;
#if XSERVER_LIBPCIACCESS
struct pci_device *PciInfo;
#else
pciVideoPtr PciInfo;
PCITAG PciTag;
#endif
uint8_t variant;
unsigned int BR[20];

13
src/i830_bios.c
View File

@ -218,7 +218,6 @@ i830_bios_init(ScrnInfoPtr pScrn)
int ret;
int size;
#if XSERVER_LIBPCIACCESS
size = pI830->PciInfo->rom_size;
if (size == 0) {
size = INTEL_VBIOS_SIZE;
@ -226,14 +225,10 @@ i830_bios_init(ScrnInfoPtr pScrn)
"libpciaccess reported 0 rom size, guessing %dkB\n",
size / 1024);
}
#else
size = INTEL_VBIOS_SIZE;
#endif
bios = xalloc(size);
if (bios == NULL)
return -1;
#if XSERVER_LIBPCIACCESS
ret = pci_device_read_rom (pI830->PciInfo, bios);
if (ret != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@ -242,14 +237,6 @@ i830_bios_init(ScrnInfoPtr pScrn)
xfree (bios);
return -1;
}
#else
/* xf86ReadPciBIOS returns the length read */
ret = xf86ReadPciBIOS(0, pI830->PciTag, 0, bios, size);
if (ret <= 0) {
xfree (bios);
return -1;
}
#endif
vbt_off = INTEL_BIOS_16(0x1a);
if (vbt_off >= size) {

9
src/i830_display.c
View File

@ -1350,11 +1350,7 @@ i830_get_core_clock_speed(ScrnInfoPtr pScrn)
else if (IS_I915GM(pI830)) {
uint16_t gcfgc;
#if XSERVER_LIBPCIACCESS
pci_device_cfg_read_u16 (pI830->PciInfo, &gcfgc, I915_GCFGC);
#else
gcfgc = pciReadWord(pI830->PciTag, I915_GCFGC);
#endif
if (gcfgc & I915_LOW_FREQUENCY_ENABLE)
return 133000;
else {
@ -1369,14 +1365,9 @@ i830_get_core_clock_speed(ScrnInfoPtr pScrn)
} else if (IS_I865G(pI830))
return 266000;
else if (IS_I855(pI830)) {
#if XSERVER_LIBPCIACCESS
struct pci_device *bridge = intel_host_bridge ();
uint16_t hpllcc;
pci_device_cfg_read_u16 (bridge, &hpllcc, I855_HPLLCC);
#else
PCITAG bridge = pciTag(0, 0, 0); /* This is always the host bridge */
uint16_t hpllcc = pciReadWord(bridge, I855_HPLLCC);
#endif
/* Assume that the hardware is in the high speed state. This
* should be the default.

85
src/i830_driver.c
View File

@ -389,20 +389,11 @@ static int
I830DetectMemory(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
#if !XSERVER_LIBPCIACCESS
PCITAG bridge;
#endif
uint16_t gmch_ctrl;
int memsize = 0, gtt_size;
int range;
#if XSERVER_LIBPCIACCESS
struct pci_device *bridge = intel_host_bridge ();
pci_device_cfg_read_u16(bridge, & gmch_ctrl, I830_GMCH_CTRL);
#else
bridge = pciTag(0, 0, 0); /* This is always the host bridge */
gmch_ctrl = pciReadWord(bridge, I830_GMCH_CTRL);
#endif
if (IS_I965G(pI830)) {
/* The 965 may have a GTT that is actually larger than is necessary
@ -547,15 +538,10 @@ I830DetectMemory(ScrnInfoPtr pScrn)
static Bool
I830MapMMIO(ScrnInfoPtr pScrn)
{
#if XSERVER_LIBPCIACCESS
int err;
struct pci_device *device;
#else
int mmioFlags;
#endif
I830Ptr pI830 = I830PTR(pScrn);
#if XSERVER_LIBPCIACCESS
device = pI830->PciInfo;
err = pci_device_map_range (device,
pI830->MMIOAddr,
@ -569,20 +555,6 @@ I830MapMMIO(ScrnInfoPtr pScrn)
strerror (err), err);
return FALSE;
}
#else
#if !defined(__alpha__)
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
#else
mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT | VIDMEM_SPARSE;
#endif
pI830->MMIOBase = xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pI830->PciTag,
pI830->MMIOAddr, I810_REG_SIZE);
if (!pI830->MMIOBase)
return FALSE;
#endif
/* Set up the GTT mapping for the various places it has been moved over
* time.
@ -605,7 +577,6 @@ I830MapMMIO(ScrnInfoPtr pScrn)
gttaddr = I810_MEMBASE(pI830->PciInfo, 3) & 0xFFFFFF00;
pI830->GTTMapSize = pI830->FbMapSize / 1024;
}
#if XSERVER_LIBPCIACCESS
err = pci_device_map_range (device,
gttaddr, pI830->GTTMapSize,
PCI_DEV_MAP_FLAG_WRITABLE,
@ -617,13 +588,6 @@ I830MapMMIO(ScrnInfoPtr pScrn)
strerror (err), err);
return FALSE;
}
#else
pI830->GTTBase = xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
pI830->PciTag,
gttaddr, pI830->GTTMapSize);
if (pI830->GTTBase == NULL)
return FALSE;
#endif
} else {
/* The GTT aperture on i830 is write-only. We could probably map the
* actual physical pages that back it, but leave it alone for now.
@ -640,27 +604,17 @@ I830MapMem(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
long i;
#if XSERVER_LIBPCIACCESS
struct pci_device *const device = pI830->PciInfo;
int err;
#endif
for (i = 2; i < pI830->FbMapSize; i <<= 1) ;
pI830->FbMapSize = i;
#if XSERVER_LIBPCIACCESS
err = pci_device_map_range (device, pI830->LinearAddr, pI830->FbMapSize,
PCI_DEV_MAP_FLAG_WRITABLE | PCI_DEV_MAP_FLAG_WRITE_COMBINE,
(void **) &pI830->FbBase);
if (err)
return FALSE;
#else
pI830->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
pI830->PciTag,
pI830->LinearAddr, pI830->FbMapSize);
if (!pI830->FbBase)
return FALSE;
#endif
if (pI830->ring.mem != NULL) {
pI830->ring.virtual_start = pI830->FbBase + pI830->ring.mem->offset;
@ -674,20 +628,11 @@ I830UnmapMMIO(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
#if XSERVER_LIBPCIACCESS
pci_device_unmap_range (pI830->PciInfo, pI830->MMIOBase, I810_REG_SIZE);
#else
xf86UnMapVidMem(pScrn->scrnIndex, (pointer) pI830->MMIOBase,
I810_REG_SIZE);
#endif
pI830->MMIOBase = NULL;
if (IS_I9XX(pI830)) {
#if XSERVER_LIBPCIACCESS
pci_device_unmap_range (pI830->PciInfo, pI830->GTTBase, pI830->GTTMapSize);
#else
xf86UnMapVidMem(pScrn->scrnIndex, pI830->GTTBase, pI830->GTTMapSize);
#endif
pI830->GTTBase = NULL;
}
}
@ -697,12 +642,7 @@ I830UnmapMem(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
#if XSERVER_LIBPCIACCESS
pci_device_unmap_range (pI830->PciInfo, pI830->FbBase, pI830->FbMapSize);
#else
xf86UnMapVidMem(pScrn->scrnIndex, (pointer) pI830->FbBase,
pI830->FbMapSize);
#endif
pI830->FbBase = NULL;
I830UnmapMMIO(pScrn);
return TRUE;
@ -1179,11 +1119,7 @@ i830SetHotkeyControl(ScrnInfoPtr pScrn, int mode)
*/
static Bool i830_kernel_mode_enabled(ScrnInfoPtr pScrn)
{
#if XSERVER_LIBPCIACCESS
struct pci_device *PciInfo;
#else
pciVideoPtr PciInfo;
#endif
EntityInfoPtr pEnt;
char *busIdString;
int ret;
@ -1227,11 +1163,7 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
break;
case PCI_CHIP_I855_GM:
/* Check capid register to find the chipset variant */
#if XSERVER_LIBPCIACCESS
pci_device_cfg_read_u32 (pI830->PciInfo, &capid, I85X_CAPID);
#else
capid = pciReadLong (pI830->PciTag, I85X_CAPID);
#endif
pI830->variant = (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
switch (pI830->variant) {
case I855_GM:
@ -1410,19 +1342,11 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
/* Now figure out mapsize on 8xx chips */
if (IS_I830(pI830) || IS_845G(pI830)) {
#if XSERVER_LIBPCIACCESS
uint16_t gmch_ctrl;
struct pci_device *bridge;
bridge = intel_host_bridge ();
pci_device_cfg_read_u16 (bridge, &gmch_ctrl, I830_GMCH_CTRL);
#else
PCITAG bridge;
uint16_t gmch_ctrl;
bridge = pciTag(0, 0, 0); /* This is always the host bridge */
gmch_ctrl = pciReadWord(bridge, I830_GMCH_CTRL);
#endif
if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
pI830->FbMapSize = 0x8000000;
} else {
@ -1430,12 +1354,7 @@ i830_detect_chipset(ScrnInfoPtr pScrn)
}
} else {
if (IS_I9XX(pI830)) {
#if XSERVER_LIBPCIACCESS
pI830->FbMapSize = pI830->PciInfo->regions[fb_bar].size;
#else
pI830->FbMapSize = 1UL << pciGetBaseSize(pI830->PciTag, 2, TRUE,
NULL);
#endif
} else {
/* 128MB aperture for later i8xx series. */
pI830->FbMapSize = 0x8000000;
@ -1726,10 +1645,6 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
return FALSE;
pI830->PciInfo = xf86GetPciInfoForEntity(pI830->pEnt->index);
#if !XSERVER_LIBPCIACCESS
pI830->PciTag = pciTag(pI830->PciInfo->bus, pI830->PciInfo->device,
pI830->PciInfo->func);
#endif
if (xf86RegisterResources(pI830->pEnt->index, NULL, ResNone)) {
PreInitCleanup(pScrn);

16
src/i830_lvds.c
View File

@ -207,12 +207,8 @@ i830_lvds_set_backlight_legacy(xf86OutputPtr output, int level)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
#if XSERVER_LIBPCIACCESS
pci_device_cfg_write_u8(pI830->PciInfo, level,
LEGACY_BACKLIGHT_BRIGHTNESS);
#else
pciWriteByte(pI830->PciTag, LEGACY_BACKLIGHT_BRIGHTNESS, level);
#endif
}
static int
@ -222,11 +218,7 @@ i830_lvds_get_backlight_legacy(xf86OutputPtr output)
I830Ptr pI830 = I830PTR(pScrn);
uint8_t lbb;
#if XSERVER_LIBPCIACCESS
pci_device_cfg_read_u8(pI830->PciInfo, &lbb, LEGACY_BACKLIGHT_BRIGHTNESS);
#else
lbb = pciReadByte(pI830->PciTag, LEGACY_BACKLIGHT_BRIGHTNESS);
#endif
return lbb;
}
@ -242,22 +234,14 @@ i830_lvds_set_backlight_combo(xf86OutputPtr output, int level)
uint32_t blc_pwm_ctl;
uint8_t lbb;
#if XSERVER_LIBPCIACCESS
pci_device_cfg_read_u8(pI830->PciInfo, &lbb, LEGACY_BACKLIGHT_BRIGHTNESS);
#else
lbb = pciReadByte(pI830->PciTag, LEGACY_BACKLIGHT_BRIGHTNESS);
#endif
/*
* If LBB is zero and we're shooting for a non-zero brightness level,
* we have to increase LBB by at least 1.
*/
if (!lbb && level) {
#if XSERVER_LIBPCIACCESS
pci_device_cfg_write_u8(pI830->PciInfo, 1,
LEGACY_BACKLIGHT_BRIGHTNESS);
#else
pciWriteByte(pI830->PciTag, LEGACY_BACKLIGHT_BRIGHTNESS, 1);
#endif
}
/*

8
src/reg_dumper/gtt.c
View File

@ -59,9 +59,9 @@ int main(int argc, char **argv)
else {
/* 915/945 chips has GTT range in bar 3*/
int err = 0;
err = pci_device_map_range (pI830->pci_dev,
pI830->pci_dev->regions[3].base_addr,
pI830->pci_dev->regions[3].size,
err = pci_device_map_range (pI830->PciInfo,
pI830->PciInfo->regions[3].base_addr,
pI830->PciInfo->regions[3].size,
PCI_DEV_MAP_FLAG_WRITABLE,
(void **)&gtt);
if (err != 0) {
@ -70,7 +70,7 @@ int main(int argc, char **argv)
}
}
aper_size = pI830->pci_dev->regions[2].size;
aper_size = pI830->PciInfo->regions[2].size;
for (start = 0; start < aper_size; start += KB(4)) {
uint32_t start_pte = INGTT(start);

5
src/reg_dumper/hotplug.c
View File

@ -72,10 +72,7 @@ int main(int argc, char **argv)
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
i830.PciInfo = &i830.pci_info_rec;
i830.PciInfo->chipType = dev->device_id;
i830.pci_dev = dev;
i830.PciInfo = dev;
mmio_bar = IS_I9XX((&i830)) ? 0 : 1;

5
src/reg_dumper/idle.c
View File

@ -142,10 +142,7 @@ int main(int argc, char **argv)
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
i830.PciInfo = &i830.pci_info_rec;
i830.PciInfo->chipType = dev->device_id;
i830.pci_dev = dev;
i830.PciInfo = dev;
mmio_bar = IS_I9XX((&i830)) ? 0 : 1;

6
src/reg_dumper/main.c
View File

@ -29,7 +29,6 @@
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#include <pciaccess.h>
#include <err.h>
#include "reg_dumper.h"
@ -62,10 +61,7 @@ int main(int argc, char **argv)
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
i830.PciInfo = &i830.pci_info_rec;
i830.PciInfo->chipType = dev->device_id;
i830.pci_dev = dev;
i830.PciInfo = dev;
mmio_bar = IS_I9XX((&i830)) ? 0 : 1;

9
src/reg_dumper/reg_dumper.h
View File

@ -29,6 +29,7 @@
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <pciaccess.h>
#include "common.h"
/** @file
@ -45,18 +46,12 @@ typedef char Bool;
#define X_WARNING 1
#define X_ERROR 2
struct pci_info_rec {
uint16_t chipType;
};
typedef struct _i830 {
/* Fields in common with the real pI830 */
struct pci_info_rec *PciInfo;
struct pci_device *PciInfo;
Bool use_drm_mode;
/* Fields used for setting up reg_dumper */
struct pci_device *pci_dev;
struct pci_info_rec pci_info_rec;
volatile unsigned char *mmio;
} I830Rec, *I830Ptr;

5
src/reg_dumper/util.c
View File

@ -65,10 +65,7 @@ void intel_i830rec_init(I830Ptr pI830)
if (dev->vendor_id != 0x8086)
errx(1, "Graphics card is non-intel");
pI830->PciInfo = &pI830->pci_info_rec;
pI830->PciInfo->chipType = dev->device_id;
pI830->pci_dev = dev;
pI830->PciInfo = dev;
mmio_bar = IS_I9XX(pI830) ? 0 : 1;