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Extend the error state reporting to cover ESR and decode PGTBL_ERR for 945.

This commit is contained in:
Eric Anholt 2006-12-12 13:54:49 -08:00
parent 838af10b85
commit ec45d72743
3 changed files with 92 additions and 12 deletions
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38
src/i810_reg.h
View File

@ -398,8 +398,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define EIR 0x20B0
#define EMR 0x20B4
#define ESR 0x20B8
#define IP_ERR 0x0001
#define ERROR_RESERVED 0xffc6
# define ERR_VERTEX_MAX (1 << 5) /* lpt/cst */
# define ERR_PGTBL_ERROR (1 << 4)
# define ERR_DISPLAY_OVERLAY_UNDERRUN (1 << 3)
# define ERR_MAIN_MEMORY_REFRESH (1 << 2)
# define ERR_INSTRUCTION_ERROR (1 << 0)
/* Interrupt Control Registers
@ -507,8 +510,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PGETBL_SIZE_256KB (1 << 1)
#define PGETBL_SIZE_128KB (2 << 1)
/* Register containing pge table error results, p276
/** @defgroup PGE_ERR
* @{
*/
/** Page table debug register for i845 */
#define PGE_ERR 0x2024
#define PGE_ERR_ADDR_MASK 0xFFFFF000
#define PGE_ERR_ID_MASK 0x00000038
@ -528,8 +533,33 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PGE_ERR_ILLEGAL_TRX 0x00000004
#define PGE_ERR_LOCAL_MEM 0x00000005
#define PGE_ERR_TILED 0x00000006
/** @} */
/** @defgroup PGTBL_ER
* @{
*/
/** Page table debug register for i945 */
# define PGTBL_ER 0x2024
# define PGTBL_ERR_MT_TILING (1 << 27)
# define PGTBL_ERR_MT_GTT_PTE (1 << 26)
# define PGTBL_ERR_LC_TILING (1 << 25)
# define PGTBL_ERR_LC_GTT_PTE (1 << 24)
# define PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE (1 << 23)
# define PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE (1 << 22)
# define PGTBL_ERR_CS_VERTEXDATA_GTT_PTE (1 << 21)
# define PGTBL_ERR_CS_INSTRUCTION_GTT_PTE (1 << 20)
# define PGTBL_ERR_CS_GTT (1 << 19)
# define PGTBL_ERR_OVERLAY_TILING (1 << 18)
# define PGTBL_ERR_OVERLAY_GTT_PTE (1 << 16)
# define PGTBL_ERR_DISPC_TILING (1 << 14)
# define PGTBL_ERR_DISPC_GTT_PTE (1 << 12)
# define PGTBL_ERR_DISPB_TILING (1 << 10)
# define PGTBL_ERR_DISPB_GTT_PTE (1 << 8)
# define PGTBL_ERR_DISPA_TILING (1 << 6)
# define PGTBL_ERR_DISPA_GTT_PTE (1 << 4)
# define PGTBL_ERR_HOST_PTE_DATA (1 << 1)
# define PGTBL_ERR_HOST_GTT_PTE (1 << 0)
/** @} */
/* Page table entries loaded via mmio region, p323
*/

61
src/i830_debug.c
View File

@ -637,17 +637,67 @@ Bool
i830_check_error_state(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int errors = 0, fatal = 0;
int errors = 0;
unsigned long temp, head, tail;
if (!I830IsPrimary(pScrn)) return TRUE;
/* Check first for page table errors */
temp = INREG(PGE_ERR);
temp = INREG16(ESR);
if (temp != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "PGTBL_ER is 0x%08lx\n", temp);
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"ESR is 0x%08lx%s%s%s%s\n", temp,
temp & ERR_VERTEX_MAX ? ", max vertices exceeded" : "",
temp & ERR_PGTBL_ERROR ? ", page table error" : "",
temp & ERR_DISPLAY_OVERLAY_UNDERRUN ?
", display/overlay underrun" : "",
temp & ERR_INSTRUCTION_ERROR ? ", instruction error" : "");
errors++;
}
/* Check first for page table errors */
if (!IS_I9XX(pI830)) {
temp = INREG(PGE_ERR);
if (temp != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"PGTBL_ER is 0x%08lx\n", temp);
errors++;
}
} else {
temp = INREG(PGTBL_ER);
if (temp != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"PGTBL_ER is 0x%08lx"
"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", temp,
temp & PGTBL_ERR_HOST_GTT_PTE ? ", host gtt pte" : "",
temp & PGTBL_ERR_HOST_PTE_DATA ? ", host pte data" : "",
temp & PGTBL_ERR_DISPA_GTT_PTE ? ", display A pte" : "",
temp & PGTBL_ERR_DISPA_TILING ?
", display A tiling" : "",
temp & PGTBL_ERR_DISPB_GTT_PTE ? ", display B pte" : "",
temp & PGTBL_ERR_DISPB_TILING ?
", display B tiling" : "",
temp & PGTBL_ERR_DISPC_GTT_PTE ? ", display C pte" : "",
temp & PGTBL_ERR_DISPC_TILING ?
", display C tiling" : "",
temp & PGTBL_ERR_OVERLAY_GTT_PTE ?
", overlay GTT PTE" : "",
temp & PGTBL_ERR_OVERLAY_TILING ?
", overlay tiling" : "",
temp & PGTBL_ERR_CS_GTT ? ", CS GTT" : "",
temp & PGTBL_ERR_CS_INSTRUCTION_GTT_PTE ?
", CS instruction GTT PTE" : "",
temp & PGTBL_ERR_CS_VERTEXDATA_GTT_PTE ?
", CS vertex data GTT PTE" : "",
temp & PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE ?
", BIN instruction GTT PTE" : "",
temp & PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE ?
", BIN vertex data GTT PTE" : "",
temp & PGTBL_ERR_LC_GTT_PTE ? ", LC pte" : "",
temp & PGTBL_ERR_LC_TILING ? ", LC tiling" : "",
temp & PGTBL_ERR_MT_GTT_PTE ? ", MT pte" : "",
temp & PGTBL_ERR_MT_TILING ? ", MT tiling" : "");
errors++;
}
}
temp = INREG(PGETBL_CTL);
if (!(temp & 1)) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@ -678,8 +728,5 @@ i830_check_error_state(ScrnInfoPtr pScrn)
}
#endif
if (fatal)
FatalError("i830_check_error_state: can't recover from the above\n");
return (errors != 0);
}

5
src/i830_driver.c
View File

@ -3125,7 +3125,10 @@ I830EnterVT(int scrnIndex, int flags)
if (!I830BindAGPMemory(pScrn))
return FALSE;
i830_check_error_state(pScrn);
if (i830_check_error_state(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Existing errors found in hardware state\n");
}
ResetState(pScrn, FALSE);
SetHWOperatingState(pScrn);