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Merge commit 'origin/master' into dri2 

Conflicts:
	src/i830_dri.c
	src/i830_driver.c
	src/i830_memory.c
This commit is contained in:
Kristian Høgsberg 2008-11-12 16:40:37 -05:00
parent 3dd7f0f942 a5b1e62337
commit ee87f7becc
28 changed files with 870 additions and 629 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
configure.ac
View File

@ -75,6 +75,11 @@ AC_ARG_ENABLE(xvmc, AC_HELP_STRING([--disable-xvmc],
[XVMC="$enableval"],
[XVMC=auto])
AC_ARG_ENABLE(kms, AC_HELP_STRING([--enable-kms],
[Enable kernel mode setting support [[default=no]]]),
[KMS="$enableval"],
[KMS=no])
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
@ -107,13 +112,15 @@ if test x$DRI != xno; then
[have_dristruct_h="yes"], [have_dristruct_h="no"])
AC_CHECK_FILE([${sdkdir}/damage.h],
[have_damage_h="yes"], [have_damage_h="no"])
AC_CHECK_HEADER(xf86drmMode.h,
[DRM_MODE=yes],[DRM_MODE=no]
[#include "stdint.h"])
dnl exaGetPixmapDriverPrivate required for DRM_MODE.
PKG_CHECK_MODULES(DRM_MODE, [xorg-server >= 1.5], [], [DRM_MODE=no])
if test "x$DRM_MODE" = xyes; then
AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
if test x$KMS != xno; then
AC_CHECK_HEADER(xf86drmMode.h,
[DRM_MODE=yes],[DRM_MODE=no]
[#include "stdint.h"])
dnl exaGetPixmapDriverPrivate required for DRM_MODE.
PKG_CHECK_MODULES(DRM_MODE, [xorg-server >= 1.5], [], [DRM_MODE=no])
if test "x$DRM_MODE" = xyes; then
AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
fi
fi
fi
AC_MSG_CHECKING([whether to include DRI support])

42
man/intel.man
View File

@ -134,28 +134,22 @@ other drivers.
Disable or enable XVideo support.
Default: XVideo is enabled for configurations where it is supported.
.TP
.BI "Option \*qXvPreferOverlay\*q \*q" boolean \*q
Make hardware overlay be the first XV adaptor.
The overlay behaves incorrectly in the presence of compositing, but some prefer
it due to it syncing to vblank in the absence of compositing. While most
XV-using applications have options to select which XV adaptor to use, this
option can be used to place the overlay first for applications which don't
have options for selecting adaptors.
Default: Textured video adaptor is preferred.
.TP
.BI "Option \*qLegacy3D\*q \*q" boolean \*q
Enable support for the legacy i915_dri.so 3D driver.
This will, among other things, make the 2D driver tell libGL to
load the 3D driver i915_dri.so instead of the newer i915tex_dri.so.
This option is only used for chipsets in the range i830-i945.
Default for i830-i945 series: Enabled.
Default for i810: The option is not used.
Default for i965: The option is always true.
.TP
.BI "Option \*qAperTexSize\*q \*q" integer \*q
Give the size in kiB of the AGP aperture area that is reserved for the
DRM memory manager present in i915 drm from version 1.7.0 and upwards,
and that is used with the 3D driver in Mesa from version 6.5.2 and
upwards. If the size is set too high to make room for pre-allocated
VideoRam, the driver will try to reduce it automatically. If you use only
older Mesa or DRM versions, you may set this value to zero, and
activate the legacy texture pool (see
.B "Option \*qLegacy3D\*q"
). If you run 3D programs with large texture memory requirements, you might
gain some performance by increasing this value.
Default: 32768.
.TP
Enable support for the non-GEM mode of the 3D driver on i830 and newer.
This will allocate a large static area for older Mesa to use for its texture
pool. On systems with a working GEM environment, this can be disabled to
increase the memory pool available to other graphics tasks.
Default for i830 and newer: Enabled.
Default for i810: this option is not used.
.BI "Option \*qPageFlip\*q \*q" boolean \*q
Enable support for page flipping. This should improve 3D performance at the
potential cost of worse performance with mixed 2D/3D. Also note that this gives
@ -185,6 +179,12 @@ Default: "EXA".
.BI "Option \*qModeDebug\*q \*q" boolean \*q
Enable printing of additional debugging information about modesetting to
the server log.
Default: Disabled
.TP
.BI "Option \*qFallbackDebug\*q \*q" boolean \*q
Enable printing of debugging information on acceleration fallbacks to the
server log.
Default: Disabled
.TP
.BI "Option \*qForceEnablePipeA\*q \*q" boolean \*q
Force the driver to leave pipe A enabled. May be necessary in configurations

14
src/common.h
View File

@ -343,9 +343,9 @@ extern int I810_DEBUG;
#define IS_I945G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I945_GME)
#define IS_GM45(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_GM45_GM)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G)
#define IS_G4X(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_IGD_E_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q45_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G41_G || IS_GM45(pI810))
#define IS_I965GM(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME)
#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_GM45(pI810) || IS_G4X(pI810))
#define IS_I965G(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G35_G || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_Q || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I946_GZ || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GM || DEVICE_ID(pI810->PciInfo) == PCI_CHIP_I965_GME || IS_G4X(pI810))
#define IS_G33CLASS(pI810) (DEVICE_ID(pI810->PciInfo) == PCI_CHIP_G33_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q35_G ||\
DEVICE_ID(pI810->PciInfo) == PCI_CHIP_Q33_G)
@ -356,16 +356,16 @@ extern int I810_DEBUG;
/* mark chipsets for using gfx VM offset for overlay */
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */
#define OVERLAY_NOEXIST(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810))
/* chipsets require graphics mem for hardware status page */
#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
(IS_G33CLASS(pI810) || IS_GM45(pI810) || \
(IS_G33CLASS(pI810) ||\
IS_G4X(pI810)))
/* chipsets require status page in non stolen memory */
#define HWS_NEED_NONSTOLEN(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810))
#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810))
/* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_GM45(pI810))
#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))

17
src/i810_reg.h
View File

@ -1242,7 +1242,22 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define SDVOC_HOTPLUG_INT_EN (1 << 25)
# define TV_HOTPLUG_INT_EN (1 << 18)
# define CRT_HOTPLUG_INT_EN (1 << 9)
# define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
/* must use period 64 on GM45 according to docs */
# define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
# define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
# define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
# define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
# define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
# define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
# define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
# define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
# define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
# define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
# define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
# define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
# define CRT_HOTPLUG_MASK (0x3fc) /* Bits 9-2 */
#define PORT_HOTPLUG_STAT 0x61114
# define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
@ -1577,7 +1592,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
# define TV_ENC_C0_FIX (1 << 10)
/** Bits that must be preserved by software */
# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
# define TV_FUSE_STATE_MASK (3 << 4)
/** Read-only state that reports all features enabled */
# define TV_FUSE_STATE_ENABLED (0 << 4)

16
src/i830.h
View File

@ -561,6 +561,7 @@ typedef struct _I830Rec {
Bool XvDisabled; /* Xv disabled in PreInit. */
Bool XvEnabled; /* Xv enabled for this generation. */
Bool XvPreferOverlay;
#ifdef I830_XV
int colorKey;
@ -610,8 +611,6 @@ typedef struct _I830Rec {
Bool StolenOnly;
Bool checkDevices;
/* Driver phase/state information */
Bool preinit;
Bool starting;
@ -723,6 +722,8 @@ typedef struct _I830Rec {
/* User option to ignore SDVO detect bit status, in case some outputs
not detected on SDVO, so let driver try its best. */
Bool force_sdvo_detect;
/** User option to print acceleration fallback info to the server log. */
Bool fallback_debug;
} I830Rec;
#define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
@ -755,7 +756,7 @@ extern Bool I830CursorInit(ScreenPtr pScreen);
extern void IntelEmitInvarientState(ScrnInfoPtr pScrn);
extern void I830EmitInvarientState(ScrnInfoPtr pScrn);
extern void I915EmitInvarientState(ScrnInfoPtr pScrn);
extern void I830SelectBuffer(ScrnInfoPtr pScrn, int buffer);
extern Bool I830SelectBuffer(ScrnInfoPtr pScrn, int buffer);
void i830_update_cursor_offsets(ScrnInfoPtr pScrn);
/* CRTC-based cursor functions */
@ -972,6 +973,15 @@ static inline int i830_fb_compression_supported(I830Ptr pI830)
return TRUE;
}
#define I830FALLBACK(s, arg...) \
do { \
if (I830PTR(pScrn)->fallback_debug) { \
xf86DrvMsg(pScrn->scrnIndex, X_INFO, \
"EXA fallback: " s "\n", ##arg); \
} \
return FALSE; \
} while(0)
Bool i830_pixmap_tiled(PixmapPtr p);
#define i830_exa_check_pitch_2d(p) do {\

14
src/i830_accel.c
View File

@ -192,7 +192,7 @@ I830Sync(ScrnInfoPtr pScrn)
I830EmitFlush(pScrn);
intel_batch_flush(pScrn);
intel_batch_flush(pScrn, TRUE);
if (pI830->directRenderingType > DRI_NONE) {
struct drm_i915_irq_emit emit;
@ -237,14 +237,13 @@ I830EmitFlush(ScrnInfoPtr pScrn)
flags = 0;
{
BEGIN_BATCH(2);
BEGIN_BATCH(1);
OUT_BATCH(MI_FLUSH | flags);
OUT_BATCH(MI_NOOP); /* pad to quadword */
ADVANCE_BATCH();
}
}
void
Bool
I830SelectBuffer(ScrnInfoPtr pScrn, int buffer)
{
I830Ptr pI830 = I830PTR(pScrn);
@ -253,12 +252,18 @@ I830SelectBuffer(ScrnInfoPtr pScrn, int buffer)
#ifdef XF86DRI
case I830_SELECT_BACK:
pI830->bufferOffset = pI830->back_buffer->offset;
if (pI830->back_buffer->tiling == TILE_YMAJOR)
return FALSE;
break;
case I830_SELECT_THIRD:
pI830->bufferOffset = pI830->third_buffer->offset;
if (pI830->third_buffer->tiling == TILE_YMAJOR)
return FALSE;
break;
case I830_SELECT_DEPTH:
pI830->bufferOffset = pI830->depth_buffer->offset;
if (pI830->depth_buffer->tiling == TILE_YMAJOR)
return FALSE;
break;
#endif
default:
@ -270,6 +275,7 @@ I830SelectBuffer(ScrnInfoPtr pScrn, int buffer)
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
ErrorF("I830SelectBuffer %d --> offset %x\n",
buffer, pI830->bufferOffset);
return TRUE;
}
/* The following function sets up the supported acceleration. Call it

16
src/i830_batchbuffer.c
View File

@ -156,7 +156,7 @@ intel_batch_teardown(ScrnInfoPtr pScrn)
}
void
intel_batch_flush(ScrnInfoPtr pScrn)
intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
{
I830Ptr pI830 = I830PTR(pScrn);
int ret;
@ -164,6 +164,17 @@ intel_batch_flush(ScrnInfoPtr pScrn)
if (pI830->batch_used == 0)
return;
/* If we're not using GEM, then emit a flush after each batch buffer */
if (pI830->memory_manager == NULL && !flushed) {
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (IS_I965G(pI830))
flags = 0;
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_FLUSH | flags;
pI830->batch_used += 4;
}
/* Emit a padding dword if we aren't going to be quad-word aligned. */
if ((pI830->batch_used & 4) == 0) {
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
@ -188,5 +199,6 @@ intel_batch_flush(ScrnInfoPtr pScrn)
* blockhandler. We could set this less often, but it's probably not worth
* the work.
*/
pI830->need_mi_flush = TRUE;
if (pI830->memory_manager != NULL)
pI830->need_mi_flush = TRUE;
}

8
src/i830_batchbuffer.h
View File

@ -34,7 +34,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
void intel_batch_init(ScrnInfoPtr pScrn);
void intel_batch_teardown(ScrnInfoPtr pScrn);
void intel_batch_flush(ScrnInfoPtr pScrn);
void intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed);
static inline int
intel_batch_space(I830Ptr pI830)
@ -47,7 +47,7 @@ intel_batch_require_space(ScrnInfoPtr pScrn, I830Ptr pI830, GLuint sz)
{
assert(sz < pI830->batch_bo->size - 8);
if (intel_batch_space(pI830) < sz)
intel_batch_flush(pScrn);
intel_batch_flush(pScrn, FALSE);
}
static inline void
@ -119,8 +119,8 @@ do { \
if (pI830->batch_emitting != 0) \
FatalError("%s: BEGIN_BATCH called without closing " \
"ADVANCE_BATCH\n", __FUNCTION__); \
intel_batch_require_space(pScrn, pI830, (n) * 4); \
pI830->batch_emitting = (n) * 4; \
intel_batch_require_space(pScrn, pI830, pI830->batch_emitting); \
pI830->batch_emit_start = pI830->batch_used; \
} while (0)
@ -140,7 +140,7 @@ do { \
pI830->batch_emitting); \
if ((pI830->batch_emitting > 8) && (I810_DEBUG & DEBUG_ALWAYS_SYNC)) { \
/* Note: not actually syncing, just flushing each batch. */ \
intel_batch_flush(pScrn); \
intel_batch_flush(pScrn, FALSE); \
} \
pI830->batch_emitting = 0; \
} while (0)

16
src/i830_common.h
View File

@ -124,14 +124,14 @@ typedef struct {
unsigned int rotated_tiled;
unsigned int rotated2_tiled;
int planeA_x;
int planeA_y;
int planeA_w;
int planeA_h;
int planeB_x;
int planeB_y;
int planeB_w;
int planeB_h;
int pipeA_x;
int pipeA_y;
int pipeA_w;
int pipeA_h;
int pipeB_x;
int pipeB_y;
int pipeB_w;
int pipeB_h;
/* Triple buffering */
drm_handle_t third_handle;

60
src/i830_crt.c
View File

@ -158,39 +158,55 @@ i830_crt_detect_hotplug(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t temp;
uint32_t hotplug_en, temp;
const int timeout_ms = 1000;
int starttime, curtime;
int tries = 1;
int try;
/* On 4 series, CRT detect sequence need to be done twice for safe. */
if (IS_G4X(pI830))
/* On 4 series desktop, CRT detect sequence need to be done twice
* to get a reliable result. */
if (IS_G4X(pI830) && !IS_GM45(pI830))
tries = 2;
else
tries = 1;
retry:
tries--;
hotplug_en = INREG(PORT_HOTPLUG_EN);
temp = INREG(PORT_HOTPLUG_EN);
hotplug_en &= ~CRT_HOTPLUG_MASK;
OUTREG(PORT_HOTPLUG_EN, temp | CRT_HOTPLUG_FORCE_DETECT | (1 << 5));
/* This starts the detection sequence */
hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
for (curtime = starttime = GetTimeInMillis();
(curtime - starttime) < timeout_ms; curtime = GetTimeInMillis())
{
if ((INREG(PORT_HOTPLUG_EN) & CRT_HOTPLUG_FORCE_DETECT) == 0)
break;
/* GM45 requires a longer activation period to reliably
* detect CRT
*/
if (IS_GM45(pI830))
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
/* Use the default voltage value */
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
for (try = 0; try < tries; try++) {
/* turn FORCE_DETECT on */
OUTREG(PORT_HOTPLUG_EN, hotplug_en);
/* wait for FORCE_DETECT to go off */
for (curtime = starttime = GetTimeInMillis();
(curtime - starttime) < timeout_ms;
curtime = GetTimeInMillis())
{
temp = INREG(PORT_HOTPLUG_EN);
if ((temp & CRT_HOTPLUG_FORCE_DETECT) == 0)
break;
}
}
if (tries > 0)
goto retry;
if ((INREG(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) ==
CRT_HOTPLUG_MONITOR_COLOR)
{
return TRUE;
} else {
return FALSE;
}
/* Check the status to see if both blue and green are on now */
temp = INREG(PORT_HOTPLUG_STAT);
return ((temp & CRT_HOTPLUG_MONITOR_MASK) ==
CRT_HOTPLUG_MONITOR_COLOR);
}
/**

24
src/i830_display.c
View File

@ -428,14 +428,14 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x, int y)
if (!sPriv)
return;
switch (plane) {
switch (pipe) {
case 0:
sPriv->planeA_x = x;
sPriv->planeA_y = y;
sPriv->pipeA_x = x;
sPriv->pipeA_y = y;
break;
case 1:
sPriv->planeB_x = x;
sPriv->planeB_y = y;
sPriv->pipeB_x = x;
sPriv->pipeB_y = y;
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@ -756,7 +756,7 @@ static void i830_modeset_ctl(xf86CrtcPtr crtc, int pre)
if (pI830->directRenderingType <= DRI_NONE)
return;
modeset.crtc = intel_crtc->plane;
modeset.crtc = intel_crtc->pipe;
/*
* DPMS will be called many times (especially off), but we only
@ -921,14 +921,14 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
if (!sPriv)
return;
switch (plane) {
switch (pipe) {
case 0:
sPriv->planeA_w = enabled ? crtc->mode.HDisplay : 0;
sPriv->planeA_h = enabled ? crtc->mode.VDisplay : 0;
sPriv->pipeA_w = enabled ? crtc->mode.HDisplay : 0;
sPriv->pipeA_h = enabled ? crtc->mode.VDisplay : 0;
break;
case 1:
sPriv->planeB_w = enabled ? crtc->mode.HDisplay : 0;
sPriv->planeB_h = enabled ? crtc->mode.VDisplay : 0;
sPriv->pipeB_w = enabled ? crtc->mode.HDisplay : 0;
sPriv->pipeB_h = enabled ? crtc->mode.VDisplay : 0;
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@ -1126,7 +1126,7 @@ i830_update_dsparb(ScrnInfoPtr pScrn)
/*
* FIFO entries will be split based on programmed modes
*/
if (IS_I965GM(pI830) || IS_GM45(pI830))
if (IS_I965GM(pI830))
fifo_entries = 127;
else if (IS_I9XX(pI830))
fifo_entries = 95;

150
src/i830_dri.c
View File

@ -952,7 +952,7 @@ I830DRIResume(ScreenPtr pScreen)
I830ResumeDma(pScrn);
if (!pI830->memory_manager)
I830DRIInstIrqHandler(pScrn);
I830DRIInstIrqHandler(pScrn);
return TRUE;
}
@ -1199,47 +1199,41 @@ I830DRIInitBuffers(WindowPtr pWin, RegionPtr prgn, CARD32 index)
{
ScreenPtr pScreen = pWin->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
BoxPtr pbox = REGION_RECTS(prgn);
int nbox = REGION_NUM_RECTS(prgn);
BoxPtr pbox;
int nbox;
int buffer, first_buffer, last_buffer;
if (I810_DEBUG & DEBUG_VERBOSE_DRI)
ErrorF("I830DRIInitBuffers\n");
I830SetupForSolidFill(pScrn, 0, GXcopy, -1);
while (nbox--) {
I830SelectBuffer(pScrn, I830_SELECT_BACK);
I830SubsequentSolidFillRect(pScrn, pbox->x1, pbox->y1,
pbox->x2 - pbox->x1, pbox->y2 - pbox->y1);
first_buffer = I830_SELECT_BACK;
last_buffer = I830_SELECT_DEPTH;
if (I830PTR(pScrn)->third_buffer)
last_buffer = I830_SELECT_THIRD;
if (I830PTR(pScrn)->third_buffer) {
I830SelectBuffer(pScrn, I830_SELECT_THIRD);
for (buffer = first_buffer; buffer <= last_buffer; buffer++) {
pbox = REGION_RECTS(prgn);
nbox = REGION_NUM_RECTS(prgn);
if (!I830SelectBuffer(pScrn, buffer))
continue;
if (buffer == I830_SELECT_DEPTH) {
switch (pScrn->bitsPerPixel) {
case 16:
I830SetupForSolidFill(pScrn, 0xffff, GXcopy, -1);
break;
case 32:
I830SetupForSolidFill(pScrn, 0xffffff, GXcopy, -1);
break;
}
} else
I830SetupForSolidFill(pScrn, 0, GXcopy, -1);
while (nbox--) {
I830SubsequentSolidFillRect(pScrn, pbox->x1, pbox->y1,
pbox->x2 - pbox->x1, pbox->y2 - pbox->y1);
pbox++;
}
pbox++;
}
/* Clear the depth buffer - uses 0xffff rather than 0.
*/
pbox = REGION_RECTS(prgn);
nbox = REGION_NUM_RECTS(prgn);
I830SelectBuffer(pScrn, I830_SELECT_DEPTH);
switch (pScrn->bitsPerPixel) {
case 16:
I830SetupForSolidFill(pScrn, 0xffff, GXcopy, -1);
break;
case 32:
I830SetupForSolidFill(pScrn, 0xffffff, GXcopy, -1);
break;
}
while (nbox--) {
I830SubsequentSolidFillRect(pScrn, pbox->x1, pbox->y1,
pbox->x2 - pbox->x1, pbox->y2 - pbox->y1);
pbox++;
}
I830SelectBuffer(pScrn, I830_SELECT_FRONT);
@ -1280,6 +1274,7 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
int dx = pParent->drawable.x - ptOldOrg.x;
int dy = pParent->drawable.y - ptOldOrg.y;
int buffer, first_buffer, last_buffer;
/* If the copy will overlap in Y, reverse the order */
if (dy > 0) {
@ -1361,44 +1356,47 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
/* SelectBuffer isn't really a good concept for the i810.
*/
I830EmitFlush(pScrn);
I830SetupForScreenToScreenCopy(pScrn, xdir, ydir, GXcopy, -1, -1);
for (; nbox--; pbox++) {
first_buffer = I830_SELECT_BACK;
last_buffer = I830_SELECT_DEPTH;
if (pI830->third_buffer)
last_buffer = I830_SELECT_THIRD;
int x1 = pbox->x1;
int y1 = pbox->y1;
int destx = x1 + dx;
int desty = y1 + dy;
int w = pbox->x2 - x1 + 1;
int h = pbox->y2 - y1 + 1;
if (destx < 0)
x1 -= destx, w += destx, destx = 0;
if (desty < 0)
y1 -= desty, h += desty, desty = 0;
if (destx + w > screenwidth)
w = screenwidth - destx;
if (desty + h > screenheight)
h = screenheight - desty;
if (w <= 0)
continue;
if (h <= 0)
for (buffer = first_buffer; buffer <= last_buffer; buffer++) {
if (!I830SelectBuffer(pScrn, buffer))
continue;
I830SetupForScreenToScreenCopy(pScrn, xdir, ydir, GXcopy, -1, -1);
pbox = REGION_RECTS(prgnSrc);
nbox = REGION_NUM_RECTS(prgnSrc);
for (; nbox--; pbox++) {
if (I810_DEBUG & DEBUG_VERBOSE_DRI)
ErrorF("MoveBuffers %d,%d %dx%d dx: %d dy: %d\n",
x1, y1, w, h, dx, dy);
int x1 = pbox->x1;
int y1 = pbox->y1;
int destx = x1 + dx;
int desty = y1 + dy;
int w = pbox->x2 - x1 + 1;
int h = pbox->y2 - y1 + 1;
if (destx < 0)
x1 -= destx, w += destx, destx = 0;
if (desty < 0)
y1 -= desty, h += desty, desty = 0;
if (destx + w > screenwidth)
w = screenwidth - destx;
if (desty + h > screenheight)
h = screenheight - desty;
if (w <= 0)
continue;
if (h <= 0)
continue;
if (I810_DEBUG & DEBUG_VERBOSE_DRI)
ErrorF("MoveBuffers %d,%d %dx%d dx: %d dy: %d\n",
x1, y1, w, h, dx, dy);
I830SelectBuffer(pScrn, I830_SELECT_BACK);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
if (pI830->third_buffer) {
I830SelectBuffer(pScrn, I830_SELECT_THIRD);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
}
if (!IS_I965G(pI830)) {
I830SelectBuffer(pScrn, I830_SELECT_DEPTH);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
}
}
I830SelectBuffer(pScrn, I830_SELECT_FRONT);
I830EmitFlush(pScrn);
@ -1513,14 +1511,14 @@ I830DRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
unsigned numvisible[2] = { 0, 0 };
int i, j;
crtcBox[0].x1 = sPriv->planeA_x;
crtcBox[0].y1 = sPriv->planeA_y;
crtcBox[0].x2 = crtcBox[0].x1 + sPriv->planeA_w;
crtcBox[0].y2 = crtcBox[0].y1 + sPriv->planeA_h;
crtcBox[1].x1 = sPriv->planeB_x;
crtcBox[1].y1 = sPriv->planeB_y;
crtcBox[1].x2 = crtcBox[1].x1 + sPriv->planeB_w;
crtcBox[1].y2 = crtcBox[1].y1 + sPriv->planeB_h;
crtcBox[0].x1 = sPriv->pipeA_x;
crtcBox[0].y1 = sPriv->pipeA_y;
crtcBox[0].x2 = crtcBox[0].x1 + sPriv->pipeA_w;
crtcBox[0].y2 = crtcBox[0].y1 + sPriv->pipeA_h;
crtcBox[1].x1 = sPriv->pipeB_x;
crtcBox[1].y1 = sPriv->pipeB_y;
crtcBox[1].x2 = crtcBox[1].x1 + sPriv->pipeB_w;
crtcBox[1].y2 = crtcBox[1].y1 + sPriv->pipeB_h;
for (i = 0; i < 2; i++) {
for (j = 0; j < num; j++) {
@ -1908,7 +1906,7 @@ I830DRI2DestroyBuffers(DrawablePtr pDraw, DRI2BufferPtr buffers, int count)
}
}
static void
static unsigned int
I830DRI2CopyRegion(DrawablePtr pDraw, RegionPtr pRegion,
DRI2BufferPtr pDestBuffer, DRI2BufferPtr pSrcBuffer)
{
@ -1938,11 +1936,13 @@ I830DRI2CopyRegion(DrawablePtr pDraw, RegionPtr pRegion,
/* We can't rely on getting into the block handler before the DRI
* client gets to run again so flush now. */
intel_batch_flush(pScrn);
intel_batch_flush(pScrn, TRUE);
#if ALWAYS_SYNC
I830Sync(pScrn);
#endif
drmCommandNone(pI830->drmSubFD, DRM_I915_GEM_THROTTLE);
return 1;
}
Bool I830DRI2ScreenInit(ScreenPtr pScreen)

138
src/i830_driver.c
View File

@ -301,14 +301,12 @@ typedef enum {
OPTION_XVIDEO,
OPTION_VIDEO_KEY,
OPTION_COLOR_KEY,
OPTION_CHECKDEVICES,
OPTION_MODEDEBUG,
OPTION_FALLBACKDEBUG,
OPTION_LVDS24BITMODE,
OPTION_FBC,
OPTION_TILING,
#ifdef XF86DRI
OPTION_INTELTEXPOOL,
#endif
OPTION_LEGACY3D,
OPTION_LVDSFIXEDMODE,
OPTION_TRIPLEBUFFER,
OPTION_FORCEENABLEPIPEA,
@ -316,6 +314,7 @@ typedef enum {
OPTION_XVMC,
#endif
OPTION_FORCE_SDVO_DETECT,
OPTION_PREFER_OVERLAY,
} I830Opts;
static OptionInfoRec I830Options[] = {
@ -328,13 +327,13 @@ static OptionInfoRec I830Options[] = {
{OPTION_XVIDEO, "XVideo", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_CHECKDEVICES, "CheckDevices",OPTV_BOOLEAN, {0}, FALSE},
{OPTION_MODEDEBUG, "ModeDebug", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_FALLBACKDEBUG, "FallbackDebug", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_LVDS24BITMODE, "LVDS24Bit", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_FBC, "FramebufferCompression", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_TILING, "Tiling", OPTV_BOOLEAN, {0}, TRUE},
#ifdef XF86DRI
{OPTION_INTELTEXPOOL,"Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_LEGACY3D, "Legacy3D", OPTV_BOOLEAN, {0}, FALSE},
#endif
{OPTION_LVDSFIXEDMODE, "LVDSFixedMode", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_TRIPLEBUFFER, "TripleBuffer", OPTV_BOOLEAN, {0}, FALSE},
@ -343,6 +342,7 @@ static OptionInfoRec I830Options[] = {
{OPTION_XVMC, "XvMC", OPTV_BOOLEAN, {0}, TRUE},
#endif
{OPTION_FORCE_SDVO_DETECT, "ForceSDVODetect", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_PREFER_OVERLAY, "XvPreferOverlay", OPTV_BOOLEAN, {0}, FALSE},
{-1, NULL, OPTV_NONE, {0}, FALSE}
};
/* *INDENT-ON* */
@ -359,7 +359,6 @@ const char *i830_output_type_names[] = {
static void i830AdjustFrame(int scrnIndex, int x, int y, int flags);
static Bool I830CloseScreen(int scrnIndex, ScreenPtr pScreen);
static Bool I830EnterVT(int scrnIndex, int flags);
static CARD32 I830CheckDevicesTimer(OsTimerPtr timer, CARD32 now, pointer arg);
static Bool SaveHWState(ScrnInfoPtr pScrn);
static Bool RestoreHWState(ScrnInfoPtr pScrn);
@ -502,7 +501,7 @@ I830DetectMemory(ScrnInfoPtr pScrn)
range = gtt_size + 4;
/* new 4 series hardware has seperate GTT stolen with GFX stolen */
if (IS_G4X(pI830) || IS_GM45(pI830))
if (IS_G4X(pI830))
range = 4;
if (IS_I85X(pI830) || IS_I865G(pI830) || IS_I9XX(pI830)) {
@ -637,7 +636,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
if (IS_I965G(pI830))
{
if (IS_GM45(pI830) || IS_G4X(pI830)) {
if (IS_G4X(pI830)) {
gttaddr = pI830->MMIOAddr + MB(2);
pI830->GTTMapSize = MB(2);
} else {
@ -962,7 +961,7 @@ i830_init_clock_gating(ScrnInfoPtr pScrn)
/* Disable clock gating reported to work incorrectly according to the specs.
*/
if (IS_GM45(pI830) || IS_G4X(pI830)) {
if (IS_G4X(pI830)) {
uint32_t dspclk_gate;
OUTREG(RENCLK_GATE_D1, 0);
OUTREG(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@ -1436,6 +1435,9 @@ I830GetEarlyOptions(ScrnInfoPtr pScrn)
memcpy(pI830->Options, I830Options, sizeof(I830Options));
xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, pI830->Options);
pI830->fallback_debug = xf86ReturnOptValBool(pI830->Options,
OPTION_FALLBACKDEBUG, FALSE);
if (xf86ReturnOptValBool(pI830->Options, OPTION_MODEDEBUG, FALSE)) {
pI830->debug_modes = TRUE;
} else {
@ -1568,22 +1570,8 @@ I830AccelMethodInit(ScrnInfoPtr pScrn)
}
if (pI830->directRenderingType == DRI_XF86DRI) {
pI830->allocate_classic_textures = TRUE;
from = X_PROBED;
#ifdef XF86DRI_MM
if (!IS_I965G(pI830)) {
Bool tmp;
if (xf86GetOptValBool(pI830->Options,
OPTION_INTELTEXPOOL, &tmp)) {
from = X_CONFIG;
if (!tmp)
pI830->allocate_classic_textures = FALSE;
}
}
#endif /* XF86DRI_MM */
pI830->allocate_classic_textures =
xf86ReturnOptValBool(pI830->Options, OPTION_LEGACY3D, TRUE);
}
}
#endif /* XF86DRI */
@ -1627,27 +1615,6 @@ I830AccelMethodInit(ScrnInfoPtr pScrn)
/* XXX This should go away, replaced by xf86Crtc.c support for it */
pI830->rotation = RR_Rotate_0;
/*
* Let's setup the mobile systems to check the lid status
*/
if (IS_MOBILE(pI830)) {
pI830->checkDevices = TRUE;
if (!xf86ReturnOptValBool(pI830->Options, OPTION_CHECKDEVICES, TRUE)) {
pI830->checkDevices = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitoring connected displays disabled\n");
} else
if (pI830->entityPrivate && !I830IsPrimary(pScrn) &&
!I830PTR(pI830->entityPrivate->pScrn_1)->checkDevices) {
/* If checklid is off, on the primary head, then
* turn it off on the secondary*/
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitoring connected displays disabled\n");
pI830->checkDevices = FALSE;
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Monitoring connected displays enabled\n");
} else
pI830->checkDevices = FALSE;
pI830->stolen_size = I830DetectMemory(pScrn);
return TRUE;
@ -1706,6 +1673,8 @@ I830XvInit(ScrnInfoPtr pScrn)
pI830->XvDisabled =
!xf86ReturnOptValBool(pI830->Options, OPTION_XVIDEO, TRUE);
pI830->XvPreferOverlay = xf86ReturnOptValBool(pI830->Options, OPTION_PREFER_OVERLAY, FALSE);
#ifdef I830_XV
if (xf86GetOptValInteger(pI830->Options, OPTION_VIDEO_KEY,
&(pI830->colorKey))) {
@ -2683,17 +2652,21 @@ I830BlockHandler(int i,
pScreen->BlockHandler = I830BlockHandler;
if (pScrn->vtSema && pI830->accel != ACCEL_NONE) {
Bool flushed = FALSE;
/* Emit a flush of the rendering cache, or on the 965 and beyond
* rendering results may not hit the framebuffer until significantly
* later.
*/
if (pI830->accel != ACCEL_NONE && (pI830->need_mi_flush || pI830->batch_used))
{
flushed = TRUE;
I830EmitFlush(pScrn);
}
/* Flush the batch, so that any rendering is executed in a timely
* fashion.
*/
intel_batch_flush(pScrn);
intel_batch_flush(pScrn, flushed);
#ifdef XF86DRI
if (pI830->memory_manager)
drmCommandNone(pI830->drmSubFD, DRM_I915_GEM_THROTTLE);
@ -3335,7 +3308,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
return FALSE;
}
i830_disable_render_standby(pScrn);
if (!pI830->use_drm_mode)
i830_disable_render_standby(pScrn);
DPRINTF(PFX, "assert( if(!I830EnterVT(scrnIndex, 0)) )\n");
@ -3562,8 +3536,10 @@ I830LeaveVT(int scrnIndex, int flags)
pI830->directRenderingType == DRI_XF86DRI) {
DRILock(screenInfo.screens[pScrn->scrnIndex], 0);
I830DRISetVBlankInterrupt (pScrn, FALSE);
drmCtlUninstHandler(pI830->drmSubFD);
if (!pI830->memory_manager) {
I830DRISetVBlankInterrupt (pScrn, FALSE);
drmCtlUninstHandler(pI830->drmSubFD);
}
}
#endif
@ -3763,16 +3739,14 @@ I830EnterVT(int scrnIndex, int flags)
}
#endif
/* Set the hotkey to just notify us. We can check its results periodically
* in the CheckDevicesTimer. Eventually we want the kernel to just hand us
* an input event when someone presses the button, but for now we just have
* to poll.
/* Set the hotkey to just notify us. We could check its results
* periodically and attempt to do something, but it seems like we basically
* never get results when we should, and this should all be better handled
* through ACPI putting the key events out through evdev and your desktop
* environment picking it up.
*/
i830SetHotkeyControl(pScrn, HOTKEY_DRIVER_NOTIFY);
if (pI830->checkDevices)
pI830->devicesTimer = TimerSet(NULL, 0, 1000, I830CheckDevicesTimer, pScrn);
/* Mark 3D state as being clobbered and setup the basics */
*pI830->last_3d = LAST_3D_OTHER;
IntelEmitInvarientState(pScrn);
@ -3958,21 +3932,11 @@ I830PMEvent(int scrnIndex, pmEvent event, Bool undo)
break;
/* This is currently used for ACPI */
case XF86_APM_CAPABILITY_CHANGED:
#if 0
/* If we had status checking turned on, turn it off now */
if (pI830->checkDevices) {
if (pI830->devicesTimer)
TimerFree(pI830->devicesTimer);
pI830->devicesTimer = NULL;
pI830->checkDevices = FALSE;
}
#endif
if (!I830IsPrimary(pScrn))
return TRUE;
ErrorF("I830PMEvent: Capability change\n");
I830CheckDevicesTimer(NULL, 0, pScrn);
SaveScreens(SCREEN_SAVER_FORCER, ScreenSaverReset);
if (pI830->quirk_flag & QUIRK_RESET_MODES)
xf86SetDesiredModes(pScrn);
@ -4037,44 +4001,6 @@ i830MonitorDetectDebugger(ScrnInfoPtr pScrn)
}
#endif
static CARD32
I830CheckDevicesTimer(OsTimerPtr timer, CARD32 now, pointer arg)
{
ScrnInfoPtr pScrn = (ScrnInfoPtr) arg;
I830Ptr pI830 = I830PTR(pScrn);
uint8_t gr18;
if (!pScrn->vtSema)
return 1000;
#if 0
i830MonitorDetectDebugger(pScrn);
#endif
/* Check for a hotkey press report from the BIOS. */
gr18 = pI830->readControl(pI830, GRX, 0x18);
if ((gr18 & (HOTKEY_TOGGLE | HOTKEY_SWITCH)) != 0) {
/* The user has pressed the hotkey requesting a toggle or switch.
* Re-probe our connected displays and turn on whatever we find.
*
* In the future, we want the hotkey to dump down to a user app which
* implements a sensible policy using RandR-1.2. For now, all we get
* is this.
*/
xf86ProbeOutputModes (pScrn, 0, 0);
xf86SetScrnInfoModes (pScrn);
xf86DiDGAReInit (pScrn->pScreen);
xf86SwitchMode(pScrn->pScreen, pScrn->currentMode);
/* Clear the BIOS's hotkey press flags */
gr18 &= ~(HOTKEY_TOGGLE | HOTKEY_SWITCH);
pI830->writeControl(pI830, GRX, 0x18, gr18);
}
return 1000;
}
void
i830WaitSync(ScrnInfoPtr pScrn)
{

31
src/i830_exa.c
View File

@ -37,26 +37,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i810_reg.h"
#include <string.h>
#ifdef I830DEBUG
#define DEBUG_I830FALLBACK 1
#endif
#define ALWAYS_SYNC 0
#define ALWAYS_FLUSH 0
#ifdef DEBUG_I830FALLBACK
#define I830FALLBACK(s, arg...) \
do { \
DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
return FALSE; \
} while(0)
#else
#define I830FALLBACK(s, arg...) \
do { \
return FALSE; \
} while(0)
#endif
const int I830CopyROP[16] =
{
ROP_0, /* GXclear */
@ -248,11 +231,11 @@ I830EXASolid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
static void
I830EXADoneSolid(PixmapPtr pPixmap)
{
#if ALWAYS_SYNC || ALWAYS_FLUSH || 1
#if ALWAYS_SYNC || ALWAYS_FLUSH
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
#if ALWAYS_FLUSH || 1
intel_batch_flush(pScrn);
#if ALWAYS_FLUSH
intel_batch_flush(pScrn, FALSE);
#endif
#if ALWAYS_SYNC
I830Sync(pScrn);
@ -353,7 +336,7 @@ I830EXADoneCopy(PixmapPtr pDstPixmap)
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
#if ALWAYS_FLUSH
intel_batch_flush(pScrn);
intel_batch_flush(pScrn, FALSE);
#endif
#if ALWAYS_SYNC
I830Sync(pScrn);
@ -374,7 +357,7 @@ i830_done_composite(PixmapPtr pDst)
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
#if ALWAYS_FLUSH
intel_batch_flush(pScrn);
intel_batch_flush(pScrn, FALSE);
#endif
#if ALWAYS_SYNC
I830Sync(pScrn);
@ -530,7 +513,7 @@ static Bool I830EXAPrepareAccess(PixmapPtr pPix, int index)
return TRUE;
}
intel_batch_flush(scrn);
intel_batch_flush(scrn, FALSE);
if (i830->need_sync) {
I830Sync(scrn);
i830->need_sync = FALSE;
@ -771,7 +754,7 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
intel_batch_flush(scrn);
intel_batch_flush(scrn, FALSE);
if (i830->need_sync) {
I830Sync(scrn);
i830->need_sync = FALSE;

4
src/i830_hdmi.c
View File

@ -142,11 +142,11 @@ i830_hdmi_detect(xf86OutputPtr output)
xf86OutputStatus status;
xf86MonPtr edid_mon;
/* For G4X, PEG_BAND_GAP_DATA 3:0 must first be written 0xd.
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 0xd.
* Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
if (IS_G4X(pI830)) {
if (IS_G4X(pI830) && !IS_GM45(pI830)) {
temp = INREG(PEG_BAND_GAP_DATA);
OUTREG(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}

29
src/i830_memory.c
View File

@ -393,6 +393,7 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
int dri_major, dri_minor, dri_patch;
struct drm_i915_getparam gp;
int has_gem;
int has_dri;
#endif
start = xcalloc(1, sizeof(*start));
@ -431,23 +432,33 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
pI830->memory_list = start;
#ifdef XF86DRI
if (pI830->directRenderingType == DRI_XF86DRI)
has_gem = FALSE;
has_dri = FALSE;
if (pI830->directRenderingType == DRI_XF86DRI &&
xf86LoaderCheckSymbol ("DRIQueryVersion"))
{
DRIQueryVersion(&dri_major, &dri_minor, &dri_patch);
has_dri = TRUE;
}
has_gem = 0;
gp.param = I915_PARAM_HAS_GEM;
gp.value = &has_gem;
(void)drmCommandWriteRead(pI830->drmSubFD, DRM_I915_GETPARAM,
&gp, sizeof(gp));
if (pI830->directRenderingType >= DRI_XF86DRI)
{
has_gem = FALSE;
gp.param = I915_PARAM_HAS_GEM;
gp.value = &has_gem;
(void)drmCommandWriteRead(pI830->drmSubFD, DRM_I915_GETPARAM,
&gp, sizeof(gp));
}
/* Now that we have our manager set up, initialize the kernel MM if
* possible, covering almost all of the aperture. We need libdri interface
* 5.4 or newer so we can rely on the lock being held after DRIScreenInit,
* rather than after DRIFinishScreenInit.
*/
if ((pI830->directRenderingType == DRI_XF86DRI && has_gem &&
(dri_major > 5 || (dri_major == 5 && dri_minor >= 4))) ||
if ((pI830->directRenderingType == DRI_XF86DRI && has_gem && has_dri &&
(dri_major > 5 || (dri_major == 5 && dri_minor >= 4))) ||
(pI830->directRenderingType == DRI_DRI2 && has_gem))
{
int mmsize;

5
src/i830_quirks.c
View File

@ -255,6 +255,8 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I965_GM, 0x1028, 0x0286, quirk_ignore_tv },
/* Dell Vostro A840 (LP: #235155) */
{ PCI_CHIP_I965_GM, 0x1028, 0x0298, quirk_ignore_tv },
/* Dell Studio Hybrid */
{ PCI_CHIP_I965_GM, 0x1028, 0x0279, quirk_ignore_lvds },
/* Lenovo Napa TV (use dmi)*/
{ PCI_CHIP_I945_GM, 0x17aa, SUBSYS_ANY, quirk_lenovo_tv_dmi },
@ -333,6 +335,9 @@ static i830_quirk i830_quirk_list[] = {
{ PCI_CHIP_I855_GM, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
{ PCI_CHIP_845_G, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
/* Asus Eee Box has no LVDS */
{ PCI_CHIP_I945_GME, 0x1043, 0x1252, quirk_ignore_lvds },
{ 0, 0, 0, NULL },
};

21
src/i830_render.c
View File

@ -34,23 +34,6 @@
#include "i830.h"
#include "i830_reg.h"
#ifdef I830DEBUG
#define DEBUG_I830FALLBACK 1
#endif
#ifdef DEBUG_I830FALLBACK
#define I830FALLBACK(s, arg...) \
do { \
DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
return FALSE; \
} while(0)
#else
#define I830FALLBACK(s, arg...) \
do { \
return FALSE; \
} while(0)
#endif
struct blendinfo {
Bool dst_alpha;
Bool src_alpha;
@ -160,6 +143,8 @@ static struct formatinfo i830_tex_formats[] = {
static Bool i830_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
@ -227,6 +212,7 @@ static uint32_t i830_get_blend_cntl(int op, PicturePtr pMask,
static Bool i830_check_composite_texture(PicturePtr pPict, int unit)
{
ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
@ -371,6 +357,7 @@ Bool
i830_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
uint32_t tmp1;
/* Check for unsupported compositing operations. */

7
src/i830_sdvo.c
View File

@ -231,10 +231,12 @@ const static struct _sdvo_cmd_name {
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODER_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
/* HDMI op code */
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
@ -1417,6 +1419,7 @@ i830_sdvo_dump_device(xf86OutputPtr output)
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SUPPORTED_TV_FORMATS);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_TV_FORMAT);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS);
i830_sdvo_dump_cmd(output, SDVO_CMD_GET_SUPP_ENCODE);
@ -1495,7 +1498,9 @@ i830_sdvo_get_ddc_modes(xf86OutputPtr output)
intel_output = crt->driver_private;
if (intel_output->type == I830_OUTPUT_ANALOG &&
crt->funcs->detect(crt) == XF86OutputStatusDisconnected) {
I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOA, "CRTDDC_A");
edid_mon = xf86OutputGetEDID(crt, intel_output->pDDCBus);
xf86DestroyI2CBusRec(intel_output->pDDCBus, TRUE, TRUE);
}
if (edid_mon) {
xf86OutputSetEDID(output, edid_mon);

137
src/i830_sdvo_regs.h
View File

@ -50,8 +50,8 @@ struct i830_sdvo_caps {
uint8_t vendor_id;
uint8_t device_id;
uint8_t device_rev_id;
uint8_t sdvo_version_major;
uint8_t sdvo_version_minor;
uint8_t sdvo_version_major;
unsigned int sdvo_input_count:2;
unsigned int smooth_scaling:1;
unsigned int sharp_scaling:1;
@ -210,7 +210,8 @@ struct i830_sdvo_in_out_map {
struct i830_sdvo_get_interrupt_event_source_response {
uint16_t interrupt_status;
unsigned int ambient_light_interrupt:1;
unsigned int pad:7;
unsigned int hdmi_audio_encrypt_change:1;
unsigned int pad:6;
} __attribute__((packed));
/**
@ -336,15 +337,15 @@ struct i830_sdvo_tv_format {
unsigned int hdtv_std_smpte_240m_1080i_60:1;
unsigned int hdtv_std_smpte_260m_1080i_59:1;
unsigned int hdtv_std_smpte_260m_1080i_60:1;
unsigned int hdtv_std_smpte_270m_1080i_50:1;
unsigned int hdtv_std_smpte_274m_1080i_50:1;
unsigned int hdtv_std_smpte_274m_1080i_59:1;
unsigned int hdtv_std_smpte_274m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080p_23:1;
unsigned int hdtv_std_smpte_274m_1080p_24:1;
unsigned int hdtv_std_smpte_274m_1080p_25:1;
unsigned int hdtv_std_smpte_274m_1080p_29:1;
unsigned int hdtv_std_smpte_274m_1080p_30:1;
unsigned int hdtv_std_smpte_274m_1080p_50:1;
unsigned int hdtv_std_smpte_274m_1080p_59:1;
@ -356,7 +357,7 @@ struct i830_sdvo_tv_format {
unsigned int hdtv_std_smpte_296m_720p_50:1;
unsigned int hdtv_std_smpte_293m_480p_59:1;
unsigned int hdtv_std_smpte_270m_480i_59:1;
unsigned int hdtv_std_smpte_170m_480i_59:1;
unsigned int hdtv_std_iturbt601_576i_50:1;
unsigned int hdtv_std_iturbt601_576p_50:1;
unsigned int hdtv_std_eia_7702a_480i_60:1;
@ -385,7 +386,17 @@ struct i830_sdvo_sdtv_resolution_request {
unsigned int pal_n:1;
unsigned int pal_nc:1;
unsigned int pal_60:1;
unsigned int secam_b:1;
unsigned int secam_d:1;
unsigned int secam_g:1;
unsigned int secam_k:1;
unsigned int secam_k1:1;
unsigned int secam_l:1;
unsigned int secam_60:1;
unsigned int pad:5;
} __attribute__((packed));
struct i830_sdvo_sdtv_resolution_reply {
unsigned int res_320x200:1;
unsigned int res_320x240:1;
@ -401,6 +412,7 @@ struct i830_sdvo_sdtv_resolution_reply {
unsigned int res_720x480:1;
unsigned int res_720x540:1;
unsigned int res_720x576:1;
unsigned int res_768x576:1;
unsigned int res_800x600:1;
unsigned int res_832x624:1;
@ -410,13 +422,120 @@ struct i830_sdvo_sdtv_resolution_reply {
unsigned int pad:5;
} __attribute__((packed));
/* Get supported resolution with squire pixel aspect ratio that can be
scaled for the requested HDTV format */
#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
struct i830_sdvo_hdtv_resolution_request {
unsigned int hdtv_std_smpte_240m_1080i_59:1;
unsigned int hdtv_std_smpte_240m_1080i_60:1;
unsigned int hdtv_std_smpte_260m_1080i_59:1;
unsigned int hdtv_std_smpte_260m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080i_50:1;
unsigned int hdtv_std_smpte_274m_1080i_59:1;
unsigned int hdtv_std_smpte_274m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080p_23:1;
unsigned int hdtv_std_smpte_274m_1080p_24:1;
unsigned int hdtv_std_smpte_274m_1080p_25:1;
unsigned int hdtv_std_smpte_274m_1080p_29:1;
unsigned int hdtv_std_smpte_274m_1080p_30:1;
unsigned int hdtv_std_smpte_274m_1080p_50:1;
unsigned int hdtv_std_smpte_274m_1080p_59:1;
unsigned int hdtv_std_smpte_274m_1080p_60:1;
unsigned int hdtv_std_smpte_295m_1080i_50:1;
unsigned int hdtv_std_smpte_295m_1080p_50:1;
unsigned int hdtv_std_smpte_296m_720p_59:1;
unsigned int hdtv_std_smpte_296m_720p_60:1;
unsigned int hdtv_std_smpte_296m_720p_50:1;
unsigned int hdtv_std_smpte_293m_480p_59:1;
unsigned int hdtv_std_smpte_170m_480i_59:1;
unsigned int hdtv_std_iturbt601_576i_50:1;
unsigned int hdtv_std_iturbt601_576p_50:1;
unsigned int hdtv_std_eia_7702a_480i_60:1;
unsigned int hdtv_std_eia_7702a_480p_60:1;
unsigned int pad:6;
} __attribute__((packed));
struct i830_sdvo_hdtv_resolution_reply {
unsigned int res_640x480:1;
unsigned int res_800x600:1;
unsigned int res_1024x768:1;
unsigned int res_1280x960:1;
unsigned int res_1400x1050:1;
unsigned int res_1600x1200:1;
unsigned int res_1920x1440:1;
unsigned int res_2048x1536:1;
unsigned int res_2560x1920:1;
unsigned int res_3200x2400:1;
unsigned int res_3840x2880:1;
unsigned int pad1:5;
unsigned int res_848x480:1;
unsigned int res_1064x600:1;
unsigned int res_1280x720:1;
unsigned int res_1360x768:1;
unsigned int res_1704x960:1;
unsigned int res_1864x1050:1;
unsigned int res_1920x1080:1;
unsigned int res_2128x1200:1;
unsigned int res_2560x1400:1;
unsigned int res_2728x1536:1;
unsigned int res_3408x1920:1;
unsigned int res_4264x2400:1;
unsigned int res_5120x2880:1;
unsigned int pad2:3;
unsigned int res_768x480:1;
unsigned int res_960x600:1;
unsigned int res_1152x720:1;
unsigned int res_1124x768:1;
unsigned int res_1536x960:1;
unsigned int res_1680x1050:1;
unsigned int res_1728x1080:1;
unsigned int res_1920x1200:1;
unsigned int res_2304x1440:1;
unsigned int res_2456x1536:1;
unsigned int res_3072x1920:1;
unsigned int res_3840x2400:1;
unsigned int res_4608x2880:1;
unsigned int pad3:3;
unsigned int res_1280x1024:1;
unsigned int pad4:7;
unsigned int res_1280x768:1;
unsigned int pad5:7;
} __attribute__((packed));
/* Get supported power state returns info for encoder and monitor, rely on
last SetTargetInput and SetTargetOutput calls */
#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
/* Get power state returns info for encoder and monitor, rely on last
SetTargetInput and SetTargetOutput calls */
#define SDVO_CMD_GET_POWER_STATE 0x2b
/* Set encoder power state */
#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
# define SDVO_ENCODER_STATE_ON (1 << 0)
# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
# define SDVO_ENCODER_STATE_OFF (1 << 3)
# define SDVO_MONITOR_STATE_ON (1 << 4)
# define SDVO_MONITOR_STATE_STANDBY (1 << 5)
# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
# define SDVO_MONITOR_STATE_OFF (1 << 7)
/* Set display power state */
#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
# define SDVO_DISPLAY_STATE_ON (1 << 0)
# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
# define SDVO_DISPLAY_STATE_OFF (1 << 3)
#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
struct i830_sdvo_enhancements_reply {
@ -447,7 +566,7 @@ struct i830_sdvo_enhancements_reply {
#define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52
#define SDVO_CMD_GET_MAX_SATURATION 0x55
#define SDVO_CMD_GET_MAX_HUE 0x58
#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5c
#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
@ -461,8 +580,8 @@ struct i830_sdvo_enhancement_limits_reply {
uint16_t default_value;
} __attribute__((packed));
#define SDVO_CMD_GET_FLICKER_FITER 0x4d
#define SDVO_CMD_SET_FLICKER_FITER 0x4e
#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
#define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50
#define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51
#define SDVO_CMD_GET_2D_FLICKER_FITER 0x53

216
src/i830_tv.c
View File

@ -144,7 +144,7 @@ static const uint32_t filter_table[] = {
0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
0x28003100, 0x28002F00, 0x00003100, 0x36403000,
0x28003100, 0x28002F00, 0x00003100, 0x36403000,
0x2D002CC0, 0x30003640, 0x2D0036C0,
0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
@ -215,7 +215,7 @@ typedef struct {
*
* The constants below were all computed using a 107.520MHz clock
*/
/**
* Register programming values for TV modes.
*
@ -225,7 +225,7 @@ typedef struct {
const static tv_mode_t tv_modes[] = {
{
.name = "NTSC-M",
.clock = 107520,
.clock = 108000,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@ -239,7 +239,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@ -249,12 +249,12 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 3.5800000 actual 3.5800000 clock 107.52 */
.dda1_inc = 136,
.dda2_inc = 7624, .dda2_size = 20013,
.dda1_inc = 135,
.dda2_inc = 20800, .dda2_size = 27456,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_4,
.pal_burst = FALSE,
@ -276,7 +276,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "NTSC-443",
.clock = 107520,
.clock = 108000,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@ -289,7 +289,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@ -299,15 +299,15 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 4.4336180 actual 4.4336180 clock 107.52 */
.dda1_inc = 168,
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
.dda2_inc = 4093, .dda2_size = 27456,
.dda3_inc = 310, .dda3_size = 525,
.sc_reset = TV_SC_RESET_NEVER,
.pal_burst = FALSE,
.composite_levels = { .blank = 225, .black = 267, .burst = 113 },
.composite_color = {
@ -326,7 +326,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "NTSC-J",
.clock = 107520,
.clock = 108000,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@ -340,7 +340,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@ -350,12 +350,12 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 3.5800000 actual 3.5800000 clock 107.52 */
.dda1_inc = 136,
.dda2_inc = 7624, .dda2_size = 20013,
.dda1_inc = 135,
.dda2_inc = 20800, .dda2_size = 27456,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_4,
.pal_burst = FALSE,
@ -377,7 +377,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "PAL-M",
.clock = 107520,
.clock = 108000,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@ -391,7 +391,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 20, .vi_end_f2 = 21,
@ -401,15 +401,15 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 72, .hburst_len = 34,
.vburst_start_f1 = 9, .vburst_end_f1 = 240,
.vburst_start_f2 = 10, .vburst_end_f2 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f3 = 9, .vburst_end_f3 = 240,
.vburst_start_f4 = 10, .vburst_end_f4 = 240,
/* desired 3.5800000 actual 3.5800000 clock 107.52 */
.dda1_inc = 136,
.dda2_inc = 7624, .dda2_size = 20013,
.dda1_inc = 135,
.dda2_inc = 16704, .dda2_size = 27456,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_4,
.pal_burst = FALSE,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
.composite_levels = { .blank = 225, .black = 267, .burst = 113 },
.composite_color = {
@ -429,7 +429,7 @@ const static tv_mode_t tv_modes[] = {
{
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = "PAL-N",
.clock = 107520,
.clock = 108000,
.refresh = 25.0,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
@ -443,24 +443,24 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 24, .vi_end_f2 = 25,
.nbr_end = 286,
.burst_ena = TRUE,
.hburst_start = 73, .hburst_len = 34,
.hburst_start = 73, .hburst_len = 34,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
.vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f4 = 9, .vburst_end_f4 = 285,
/* desired 4.4336180 actual 4.4336180 clock 107.52 */
.dda1_inc = 168,
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.dda1_inc = 135,
.dda2_inc = 23578, .dda2_size = 27648,
.dda3_inc = 134, .dda3_size = 625,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
@ -482,12 +482,12 @@ const static tv_mode_t tv_modes[] = {
{
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = "PAL",
.clock = 107520,
.clock = 108000,
.refresh = 25.0,
.oversample = TV_OVERSAMPLE_8X,
.component_only = 0,
.hsync_end = 64, .hblank_end = 128,
.hsync_end = 64, .hblank_end = 142,
.hblank_start = 844, .htotal = 863,
.progressive = FALSE, .trilevel_sync = FALSE,
@ -495,7 +495,7 @@ const static tv_mode_t tv_modes[] = {
.vsync_start_f1 = 5, .vsync_start_f2 = 6,
.vsync_len = 5,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 15,
.vi_end_f1 = 24, .vi_end_f2 = 25,
@ -505,13 +505,13 @@ const static tv_mode_t tv_modes[] = {
.hburst_start = 73, .hburst_len = 32,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
.vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f4 = 9, .vburst_end_f4 = 285,
/* desired 4.4336180 actual 4.4336180 clock 107.52 */
.dda1_inc = 168,
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.dda2_inc = 4122, .dda2_size = 27648,
.dda3_inc = 67, .dda3_size = 625,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
@ -532,7 +532,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "480p@59.94Hz",
.clock = 107520,
.clock = 107520,
.refresh = 59.94,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
@ -540,7 +540,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 64, .hblank_end = 122,
.hblank_start = 842, .htotal = 857,
.progressive = TRUE,.trilevel_sync = FALSE,
.progressive = TRUE, .trilevel_sync = FALSE,
.vsync_start_f1 = 12, .vsync_start_f2 = 12,
.vsync_len = 12,
@ -548,7 +548,7 @@ const static tv_mode_t tv_modes[] = {
.veq_ena = FALSE,
.vi_end_f1 = 44, .vi_end_f2 = 44,
.nbr_end = 496,
.nbr_end = 479,
.burst_ena = FALSE,
@ -556,7 +556,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "480p@60Hz",
.clock = 107520,
.clock = 107520,
.refresh = 60.0,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
@ -564,7 +564,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 64, .hblank_end = 122,
.hblank_start = 842, .htotal = 856,
.progressive = TRUE,.trilevel_sync = FALSE,
.progressive = TRUE, .trilevel_sync = FALSE,
.vsync_start_f1 = 12, .vsync_start_f2 = 12,
.vsync_len = 12,
@ -572,7 +572,7 @@ const static tv_mode_t tv_modes[] = {
.veq_ena = FALSE,
.vi_end_f1 = 44, .vi_end_f2 = 44,
.nbr_end = 496,
.nbr_end = 479,
.burst_ena = FALSE,
@ -580,7 +580,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "576p",
.clock = 107520,
.clock = 107520,
.refresh = 50.0,
.oversample = TV_OVERSAMPLE_4X,
.component_only = 1,
@ -588,7 +588,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 64, .hblank_end = 139,
.hblank_start = 859, .htotal = 863,
.progressive = TRUE, .trilevel_sync = FALSE,
.progressive = TRUE, .trilevel_sync = FALSE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@ -604,7 +604,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "720p@60Hz",
.clock = 148800,
.clock = 148800,
.refresh = 60.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@ -612,7 +612,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1649,
.progressive = TRUE, .trilevel_sync = TRUE,
.progressive = TRUE, .trilevel_sync = TRUE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@ -628,7 +628,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "720p@59.94Hz",
.clock = 148800,
.clock = 148800,
.refresh = 59.94,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@ -636,7 +636,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1651,
.progressive = TRUE, .trilevel_sync = TRUE,
.progressive = TRUE, .trilevel_sync = TRUE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@ -652,7 +652,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "720p@50Hz",
.clock = 148800,
.clock = 148800,
.refresh = 50.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@ -660,7 +660,7 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 80, .hblank_end = 300,
.hblank_start = 1580, .htotal = 1979,
.progressive = TRUE, .trilevel_sync = TRUE,
.progressive = TRUE, .trilevel_sync = TRUE,
.vsync_start_f1 = 10, .vsync_start_f2 = 10,
.vsync_len = 10,
@ -677,7 +677,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "1080i@50Hz",
.clock = 148800,
.clock = 148800,
.refresh = 25.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@ -685,14 +685,13 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2639,
.progressive = FALSE, .trilevel_sync = TRUE,
.progressive = FALSE, .trilevel_sync = TRUE,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
@ -703,7 +702,7 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "1080i@60Hz",
.clock = 148800,
.clock = 148800,
.refresh = 30.0,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
@ -711,15 +710,14 @@ const static tv_mode_t tv_modes[] = {
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2199,
.progressive = FALSE, .trilevel_sync = TRUE,
.progressive = FALSE, .trilevel_sync = TRUE,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
@ -729,24 +727,24 @@ const static tv_mode_t tv_modes[] = {
},
{
.name = "1080i@59.94Hz",
.clock = 148800,
.clock = 148800,
.refresh = 29.97,
.oversample = TV_OVERSAMPLE_2X,
.component_only = 1,
.hsync_end = 88, .hblank_end = 235,
.hblank_start = 2155, .htotal = 2200,
.hblank_start = 2155, .htotal = 2201,
.progressive = FALSE, .trilevel_sync = TRUE,
.progressive = FALSE, .trilevel_sync = TRUE,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_start_f1 = 4, .vsync_start_f2 = 5,
.vsync_len = 10,
.veq_ena = TRUE, .veq_start_f1 = 4,
.veq_start_f2 = 4, .veq_len = 10,
.veq_start_f2 = 4, .veq_len = 10,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.vi_end_f1 = 21, .vi_end_f2 = 22,
.nbr_end = 539,
.burst_ena = FALSE,
@ -758,7 +756,7 @@ const static tv_mode_t tv_modes[] = {
#define NUM_TV_MODES sizeof(tv_modes) / sizeof (tv_modes[0])
static const video_levels_t component_level = {
.blank = 279, .black = 279
.blank = 279, .black = 279, .burst = 0,
};
static const color_conversion_t sdtv_component_color = {
@ -929,8 +927,8 @@ static const tv_mode_t *
i830_tv_mode_lookup (char *tv_format)
{
int i;
for (i = 0; i < sizeof(tv_modes) / sizeof (tv_modes[0]); i++)
for (i = 0; i < sizeof(tv_modes) / sizeof (tv_modes[0]); i++)
{
const tv_mode_t *tv_mode = &tv_modes[i];
@ -953,7 +951,7 @@ static int
i830_tv_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
{
const tv_mode_t *tv_mode = i830_tv_mode_find (output);
if (tv_mode && fabs (tv_mode->refresh - xf86ModeVRefresh (mode)) < 1.0)
return MODE_OK;
return MODE_CLOCK_RANGE;
@ -971,8 +969,8 @@ i830_tv_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
if (!tv_mode)
return FALSE;
for (i = 0; i < xf86_config->num_output; i++)
for (i = 0; i < xf86_config->num_output; i++)
{
xf86OutputPtr other_output = xf86_config->output[i];
@ -1040,11 +1038,12 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
const video_levels_t *video_levels;
const color_conversion_t *color_conversion;
Bool burst_ena;
if (!tv_mode)
return; /* can't happen (mode_prepare prevents this) */
tv_ctl = 0;
tv_ctl = INREG(TV_CTL);
tv_ctl &= TV_CTL_SAVE;
switch (dev_priv->type) {
default:
@ -1181,7 +1180,9 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
(i830_float_to_csc(color_conversion->bv) << 16) |
(i830_float_to_luma(color_conversion->av)));
OUTREG(TV_CLR_KNOBS, 0x00606000);
/* 2.6 fixed point value for contrast and saturation modifier,
use 1 as default */
OUTREG(TV_CLR_KNOBS, 0x00404000);
OUTREG(TV_CLR_LEVEL, ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
(video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
{
@ -1207,7 +1208,7 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
i830WaitForVblank(pScrn);
/* Filter ctl must be set before TV_WIN_SIZE */
OUTREG(TV_FILTER_CTL_1, TV_AUTO_SCALE);
OUTREG(TV_FILTER_CTL_1, TV_AUTO_SCALE);
xsize = tv_mode->hblank_start - tv_mode->hblank_end;
if (tv_mode->progressive)
ysize = tv_mode->nbr_end + 1;
@ -1216,9 +1217,9 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
xpos += dev_priv->margin[TV_MARGIN_LEFT];
ypos += dev_priv->margin[TV_MARGIN_TOP];
xsize -= (dev_priv->margin[TV_MARGIN_LEFT] +
xsize -= (dev_priv->margin[TV_MARGIN_LEFT] +
dev_priv->margin[TV_MARGIN_RIGHT]);
ysize -= (dev_priv->margin[TV_MARGIN_TOP] +
ysize -= (dev_priv->margin[TV_MARGIN_TOP] +
dev_priv->margin[TV_MARGIN_BOTTOM]);
OUTREG(TV_WIN_POS, (xpos<<16)|ypos);
OUTREG(TV_WIN_SIZE, (xsize<<16)|ysize);
@ -1227,7 +1228,7 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
OUTREG(dspcntr_reg, dspcntr);
/* Flush the plane changes */
OUTREG(dspbase_reg, INREG(dspbase_reg));
}
}
j = 0;
for (i = 0; i < 60; i++)
@ -1381,7 +1382,7 @@ i830_tv_detect(xf86OutputPtr output)
i830_tv_format_configure_property (output);
#endif
}
switch (type) {
case TV_TYPE_NONE:
return XF86OutputStatusDisconnected;
@ -1394,8 +1395,8 @@ i830_tv_detect(xf86OutputPtr output)
static struct input_res {
char *name;
int w, h;
} input_res_table[] =
int w, h;
} input_res_table[] =
{
{"640x480", 640, 480},
{"800x600", 800, 600},
@ -1425,16 +1426,16 @@ i830_tv_get_modes(xf86OutputPtr output)
struct input_res *input = &input_res_table[j];
unsigned int hactive_s = input->w;
unsigned int vactive_s = input->h;
if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
continue;
if (input->w > 1024 && (!tv_mode->progressive
if (input->w > 1024 && (!tv_mode->progressive
&& !tv_mode->component_only))
continue;
mode_ptr = xnfcalloc(1, sizeof(DisplayModeRec));
mode_ptr->name = xnfalloc(strlen(input->name) + 1);
mode_ptr->name = xnfalloc(strlen(input->name) + 1);
strcpy (mode_ptr->name, input->name);
mode_ptr->HDisplay = hactive_s;
@ -1451,17 +1452,17 @@ i830_tv_get_modes(xf86OutputPtr output)
mode_ptr->VSyncEnd = mode_ptr->VSyncStart + 1;
mode_ptr->VTotal = vactive_s + 33;
mode_ptr->Clock = (int) (tv_mode->refresh *
mode_ptr->VTotal *
mode_ptr->Clock = (int) (tv_mode->refresh *
mode_ptr->VTotal *
mode_ptr->HTotal / 1000.0);
mode_ptr->type = M_T_DRIVER;
mode_ptr->next = ret;
mode_ptr->prev = NULL;
if (ret != NULL)
ret->prev = mode_ptr;
ret = mode_ptr;
}
}
return ret;
}
@ -1499,7 +1500,6 @@ i830_tv_format_set_property (xf86OutputPtr output)
return err == Success;
}
/**
* Configure the TV_FORMAT property to list only supported formats
*
@ -1515,16 +1515,16 @@ i830_tv_format_configure_property (xf86OutputPtr output)
Atom current_atoms[NUM_TV_MODES];
int num_atoms = 0;
int i;
if (!output->randr_output)
return Success;
for (i = 0; i < NUM_TV_MODES; i++)
if (!tv_modes[i].component_only || dev_priv->type == TV_TYPE_COMPONENT)
current_atoms[num_atoms++] = tv_format_name_atoms[i];
return RRConfigureOutputProperty(output->randr_output, tv_format_atom,
TRUE, FALSE, FALSE,
TRUE, FALSE, FALSE,
num_atoms, (INT32 *) current_atoms);
}
@ -1573,7 +1573,7 @@ i830_tv_create_resources(xf86OutputPtr output)
range[1] = 100;
err = RRConfigureOutputProperty(output->randr_output, margin_atoms[i],
TRUE, TRUE, FALSE, 2, range);
if (err != 0)
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRConfigureOutputProperty error, %d\n", err);
@ -1595,8 +1595,8 @@ i830_tv_set_property(xf86OutputPtr output, Atom property,
RRPropertyValuePtr value)
{
int i;
if (property == tv_format_atom)
if (property == tv_format_atom)
{
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_tv_priv *dev_priv = intel_output->dev_priv;
@ -1609,7 +1609,7 @@ i830_tv_set_property(xf86OutputPtr output, Atom property,
memcpy (&atom, value->data, 4);
name = NameForAtom (atom);
val = xalloc (strlen (name) + 1);
if (!val)
return FALSE;
@ -1652,7 +1652,7 @@ i830_tv_get_crtc(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
int pipe = !!(INREG(TV_CTL) & TV_ENC_PIPEB_SELECT);
return i830_pipe_to_crtc(pScrn, pipe);
}
#endif
@ -1712,7 +1712,7 @@ i830_tv_init(ScrnInfoPtr pScrn)
* bit, (either as a 0 or a 1), assume it doesn't really
* exist
*/
if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
(tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
return;
@ -1739,24 +1739,24 @@ i830_tv_init(ScrnInfoPtr pScrn)
dev_priv->type = TV_TYPE_UNKNOWN;
dev_priv->tv_format = NULL;
/* BIOS margin values */
dev_priv->margin[TV_MARGIN_LEFT] = 54;
dev_priv->margin[TV_MARGIN_TOP] = 36;
dev_priv->margin[TV_MARGIN_RIGHT] = 46;
dev_priv->margin[TV_MARGIN_BOTTOM] = 37;
if (output->conf_monitor)
{
char *tv_format;
tv_format = xf86findOptionValue (output->conf_monitor->mon_option_lst, "TV Format");
if (tv_format)
dev_priv->tv_format = xstrdup (tv_format);
}
if (!dev_priv->tv_format)
dev_priv->tv_format = xstrdup (tv_modes[0].name);
output->driver_private = intel_output;
output->interlaceAllowed = FALSE;
output->doubleScanAllowed = FALSE;

12
src/i830_video.c
View File

@ -611,7 +611,6 @@ I830InitVideo(ScreenPtr pScreen)
{
texturedAdaptor = I830SetupImageVideoTextured(pScreen);
if (texturedAdaptor != NULL) {
adaptors[num_adaptors++] = texturedAdaptor;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@ -625,7 +624,6 @@ I830InitVideo(ScreenPtr pScreen)
{
overlayAdaptor = I830SetupImageVideoOverlay(pScreen);
if (overlayAdaptor != NULL) {
adaptors[num_adaptors++] = overlayAdaptor;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up overlay video\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
@ -633,6 +631,16 @@ I830InitVideo(ScreenPtr pScreen)
}
I830InitOffscreenImages(pScreen);
}
if (overlayAdaptor && pI830->XvPreferOverlay)
adaptors[num_adaptors++] = overlayAdaptor;
if (texturedAdaptor)
adaptors[num_adaptors++] = texturedAdaptor;
if (overlayAdaptor && !pI830->XvPreferOverlay)
adaptors[num_adaptors++] = overlayAdaptor;
#ifdef INTEL_XVMC
if (intel_xvmc_probe(pScrn)) {
if (texturedAdaptor)

10
src/i830_xaa.c
View File

@ -314,7 +314,7 @@ I830SetupForSolidFill(ScrnInfoPtr pScrn, int color, int rop,
color, rop, planemask);
if (IS_I965G(pI830) && I830CheckTiling(pScrn)) {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 4;
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 2;
} else {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp);
}
@ -385,7 +385,7 @@ I830SetupForScreenToScreenCopy(ScrnInfoPtr pScrn, int xdir, int ydir, int rop,
xdir, ydir, rop, planemask, transparency_color);
if (IS_I965G(pI830) && I830CheckTiling(pScrn)) {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 4;
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 2;
} else {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp);
}
@ -468,7 +468,7 @@ I830SetupForMono8x8PatternFill(ScrnInfoPtr pScrn, int pattx, int patty,
pI830->BR[19] = fg;
if (IS_I965G(pI830) && I830CheckTiling(pScrn)) {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 4;
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 2;
} else {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp);
}
@ -565,7 +565,7 @@ I830SetupForScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrn,
/* Fill out register values */
if (IS_I965G(pI830) && I830CheckTiling(pScrn)) {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 4;
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 2;
} else {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp);
}
@ -671,7 +671,7 @@ I830SetupForScanlineImageWrite(ScrnInfoPtr pScrn, int rop,
/* Fill out register values */
if (IS_I965G(pI830) && I830CheckTiling(pScrn)) {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 4;
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp) >> 2;
} else {
pI830->BR[13] = (pScrn->displayWidth * pI830->cpp);
}

21
src/i915_render.c
View File

@ -35,23 +35,6 @@
#include "i915_reg.h"
#include "i915_3d.h"
#ifdef I830DEBUG
#define DEBUG_I830FALLBACK 1
#endif
#ifdef DEBUG_I830FALLBACK
#define I830FALLBACK(s, arg...) \
do { \
DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
return FALSE; \
} while(0)
#else
#define I830FALLBACK(s, arg...) \
do { \
return FALSE; \
} while(0)
#endif
struct formatinfo {
int fmt;
uint32_t card_fmt;
@ -155,6 +138,8 @@ static uint32_t i915_get_blend_cntl(int op, PicturePtr pMask,
static Bool i915_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
@ -184,6 +169,7 @@ static Bool i915_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
static Bool i915_check_composite_texture(PicturePtr pPict, int unit)
{
ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
@ -215,6 +201,7 @@ Bool
i915_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
uint32_t tmp1;
/* Check for unsupported compositing operations. */

435
src/i965_render.c
View File

@ -42,25 +42,14 @@
#include "brw_defines.h"
#include "brw_structs.h"
#ifdef I830DEBUG
#define DEBUG_I830FALLBACK 1
#endif
#ifdef DEBUG_I830FALLBACK
#define I830FALLBACK(s, arg...) \
do { \
DPRINTF(PFX, "EXA fallback: " s "\n", ##arg); \
return FALSE; \
} while(0)
#else
#define I830FALLBACK(s, arg...) \
do { \
return FALSE; \
} while(0)
#endif
#define MAX_VERTEX_PER_COMPOSITE 24
#define MAX_VERTEX_BUFFERS 256
/* 24 = 4 vertices/composite * 3 texcoords/vertex * 2 floats/texcoord
*
* This is an upper-bound based on the case of a non-affine
* transformation and with a mask, but useful for sizing all cases for
* simplicity.
*/
#define VERTEX_FLOATS_PER_COMPOSITE 24
#define VERTEX_BUFFER_SIZE (256 * VERTEX_FLOATS_PER_COMPOSITE)
struct blendinfo {
Bool dst_alpha;
@ -161,6 +150,8 @@ static void i965_get_blend_cntl(int op, PicturePtr pMask, uint32_t dst_format,
static Bool i965_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
switch (pDstPicture->format) {
case PICT_a8r8g8b8:
case PICT_x8r8g8b8:
@ -192,6 +183,7 @@ static Bool i965_get_dest_format(PicturePtr pDstPicture, uint32_t *dst_format)
static Bool i965_check_composite_texture(PicturePtr pPict, int unit)
{
ScrnInfoPtr pScrn = xf86Screens[pPict->pDrawable->pScreen->myNum];
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
@ -226,6 +218,7 @@ Bool
i965_check_composite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
PicturePtr pDstPicture)
{
ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
uint32_t tmp1;
/* Check for unsupported compositing operations. */
@ -445,14 +438,10 @@ typedef struct brw_surface_state_padded {
/**
* Gen4 rendering state buffer structure.
*
* Ideally this structure would contain static data for all of the
* combinations of state that we use for Render acceleration, and another
* buffer would be the use-and-throw-away surface and vertex data. See the
* intel-batchbuffer branch for an implementation of that. For now, it
* has the static program data, and then a changing buffer containing all
* the rest.
* This structure contains static data for all of the combinations of
* state that we use for Render acceleration.
*/
typedef struct _gen4_state {
typedef struct _gen4_static_state {
uint8_t wm_scratch[128 * PS_MAX_THREADS];
KERNEL_DECL (sip_kernel);
@ -484,10 +473,6 @@ typedef struct _gen4_state {
WM_STATE_DECL (masknoca_affine);
WM_STATE_DECL (masknoca_projective);
uint32_t binding_table[128];
struct brw_surface_state_padded surface_state[32];
/* Index by [src_filter][src_extend][mask_filter][mask_extend]. Two of
* the structs happen to add to 32 bytes.
*/
@ -504,17 +489,29 @@ typedef struct _gen4_state {
[BRW_BLENDFACTOR_COUNT];
struct brw_cc_viewport cc_viewport;
PAD64 (brw_cc_viewport, 0);
} gen4_static_state_t;
float vb[MAX_VERTEX_PER_COMPOSITE * MAX_VERTEX_BUFFERS];
} gen4_state_t;
typedef float gen4_vertex_buffer[VERTEX_BUFFER_SIZE];
typedef struct gen4_composite_op {
int op;
PicturePtr source_picture;
PicturePtr mask_picture;
PicturePtr dest_picture;
PixmapPtr source;
PixmapPtr mask;
PixmapPtr dest;
} gen4_composite_op;
/** Private data for gen4 render accel implementation. */
struct gen4_render_state {
gen4_state_t *card_state;
uint32_t card_state_offset;
gen4_static_state_t *static_state;
uint32_t static_state_offset;
dri_bo* vertex_buffer_bo;
gen4_composite_op composite_op;
int binding_table_index;
int surface_state_index;
int vb_offset;
int vertex_size;
};
@ -707,14 +704,13 @@ wm_state_init (struct brw_wm_unit_state *wm_state,
* Called at EnterVT to fill in our state buffer with any static information.
*/
static void
gen4_state_init (struct gen4_render_state *render_state)
gen4_static_state_init (gen4_static_state_t *static_state,
uint32_t static_state_offset)
{
int i, j, k, l;
gen4_state_t *card_state = render_state->card_state;
uint32_t state_base_offset = render_state->card_state_offset;
#define KERNEL_COPY(kernel) \
memcpy(card_state->kernel, kernel ## _static, sizeof(kernel ## _static))
memcpy(static_state->kernel, kernel ## _static, sizeof(kernel ## _static))
KERNEL_COPY (sip_kernel);
KERNEL_COPY (sf_kernel);
@ -730,44 +726,44 @@ gen4_state_init (struct gen4_render_state *render_state)
#undef KERNEL_COPY
/* Set up the vertex shader to be disabled (passthrough) */
memset(&card_state->vs_state, 0, sizeof(card_state->vs_state));
card_state->vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
card_state->vs_state.thread4.urb_entry_allocation_size =
memset(&static_state->vs_state, 0, sizeof(static_state->vs_state));
static_state->vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
static_state->vs_state.thread4.urb_entry_allocation_size =
URB_VS_ENTRY_SIZE - 1;
card_state->vs_state.vs6.vs_enable = 0;
card_state->vs_state.vs6.vert_cache_disable = 1;
static_state->vs_state.vs6.vs_enable = 0;
static_state->vs_state.vs6.vert_cache_disable = 1;
/* Set up the sampler border color (always transparent black) */
memset(&card_state->sampler_border_color, 0,
sizeof(card_state->sampler_border_color));
card_state->sampler_border_color.color[0] = 0; /* R */
card_state->sampler_border_color.color[1] = 0; /* G */
card_state->sampler_border_color.color[2] = 0; /* B */
card_state->sampler_border_color.color[3] = 0; /* A */
memset(&static_state->sampler_border_color, 0,
sizeof(static_state->sampler_border_color));
static_state->sampler_border_color.color[0] = 0; /* R */
static_state->sampler_border_color.color[1] = 0; /* G */
static_state->sampler_border_color.color[2] = 0; /* B */
static_state->sampler_border_color.color[3] = 0; /* A */
card_state->cc_viewport.min_depth = -1.e35;
card_state->cc_viewport.max_depth = 1.e35;
static_state->cc_viewport.min_depth = -1.e35;
static_state->cc_viewport.max_depth = 1.e35;
sf_state_init (&card_state->sf_state,
state_base_offset +
offsetof (gen4_state_t, sf_kernel));
sf_state_init (&card_state->sf_state_mask,
state_base_offset +
offsetof (gen4_state_t, sf_kernel_mask));
sf_state_init (&static_state->sf_state,
static_state_offset +
offsetof (gen4_static_state_t, sf_kernel));
sf_state_init (&static_state->sf_state_mask,
static_state_offset +
offsetof (gen4_static_state_t, sf_kernel_mask));
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
sampler_state_init (&card_state->sampler_state[i][j][k][l][0],
sampler_state_init (&static_state->sampler_state[i][j][k][l][0],
i, j,
state_base_offset +
offsetof (gen4_state_t,
static_state_offset +
offsetof (gen4_static_state_t,
sampler_border_color));
sampler_state_init (&card_state->sampler_state[i][j][k][l][1],
sampler_state_init (&static_state->sampler_state[i][j][k][l][1],
k, l,
state_base_offset +
offsetof (gen4_state_t,
static_state_offset +
offsetof (gen4_static_state_t,
sampler_border_color));
}
}
@ -777,21 +773,21 @@ gen4_state_init (struct gen4_render_state *render_state)
for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {
cc_state_init (&card_state->cc_state[i][j].state, i, j,
state_base_offset +
offsetof (gen4_state_t, cc_viewport));
cc_state_init (&static_state->cc_state[i][j].state, i, j,
static_state_offset +
offsetof (gen4_static_state_t, cc_viewport));
}
}
#define SETUP_WM_STATE(kernel, has_mask) \
wm_state_init(&card_state->wm_state_ ## kernel [i][j][k][l], \
wm_state_init(&static_state->wm_state_ ## kernel [i][j][k][l], \
has_mask, \
state_base_offset + offsetof(gen4_state_t, \
wm_scratch), \
state_base_offset + offsetof(gen4_state_t, \
ps_kernel_ ## kernel), \
state_base_offset + offsetof(gen4_state_t, \
sampler_state[i][j][k][l]));
static_state_offset + offsetof(gen4_static_state_t, \
wm_scratch), \
static_state_offset + offsetof(gen4_static_state_t, \
ps_kernel_ ## kernel), \
static_state_offset + offsetof(gen4_static_state_t, \
sampler_state[i][j][k][l]));
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
@ -860,20 +856,19 @@ sampler_state_extend_from_picture (int repeat_type)
}
/**
* Sets up the common fields for a surface state buffer for the given picture
* in the surface state buffer at index, and returns the offset within the
* state buffer for this entry.
* Sets up the common fields for a surface state buffer for the given
* picture in the given surface state buffer.
*/
static unsigned int
i965_set_picture_surface_state(ScrnInfoPtr pScrn, struct brw_surface_state *ss,
static void
i965_set_picture_surface_state(dri_bo *ss_bo, int ss_index,
PicturePtr pPicture, PixmapPtr pPixmap,
Bool is_dst)
{
I830Ptr pI830 = I830PTR(pScrn);
struct gen4_render_state *render_state= pI830->gen4_render_state;
gen4_state_t *card_state = render_state->card_state;
struct brw_surface_state_padded *ss;
struct brw_surface_state local_ss;
uint32_t offset;
dri_bo *pixmap_bo = i830_get_pixmap_bo(pPixmap);
ss = (struct brw_surface_state_padded *)ss_bo->virtual + ss_index;
/* Since ss is a pointer to WC memory, do all of our bit operations
* into a local temporary first.
@ -901,7 +896,10 @@ i965_set_picture_surface_state(ScrnInfoPtr pScrn, struct brw_surface_state *ss,
local_ss.ss0.vert_line_stride_ofs = 0;
local_ss.ss0.mipmap_layout_mode = 0;
local_ss.ss0.render_cache_read_mode = 0;
local_ss.ss1.base_addr = intel_get_pixmap_offset(pPixmap);
if (pixmap_bo != NULL)
local_ss.ss1.base_addr = pixmap_bo->offset;
else
local_ss.ss1.base_addr = intel_get_pixmap_offset(pPixmap);
local_ss.ss2.mip_count = 0;
local_ss.ss2.render_target_rotation = 0;
@ -913,22 +911,75 @@ i965_set_picture_surface_state(ScrnInfoPtr pScrn, struct brw_surface_state *ss,
memcpy(ss, &local_ss, sizeof(local_ss));
offset = (char *)ss - (char *)card_state;
assert((offset & 31) == 0);
if (pixmap_bo != NULL) {
uint32_t write_domain, read_domains;
return offset;
if (is_dst) {
write_domain = I915_GEM_DOMAIN_RENDER;
read_domains = I915_GEM_DOMAIN_RENDER;
} else {
write_domain = 0;
read_domains = I915_GEM_DOMAIN_SAMPLER;
}
dri_bo_emit_reloc(ss_bo, read_domains, write_domain,
0,
ss_index * sizeof(*ss) +
offsetof(struct brw_surface_state, ss1),
pixmap_bo);
}
}
Bool
i965_prepare_composite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
static Bool
_emit_batch_header_for_composite_internal (ScrnInfoPtr pScrn,
Bool check_twice);
/* Allocate the dynamic state needed for a composite operation,
* flushing the current batch if needed to create sufficient space.
*
* Even after flushing we check again and return FALSE if the
* operation still can't fit with an empty batch. Otherwise, returns
* TRUE.
*/
static Bool
_emit_batch_header_for_composite_check_twice (ScrnInfoPtr pScrn)
{
return _emit_batch_header_for_composite_internal (pScrn, TRUE);
}
/* Allocate the dynamic state needed for a composite operation,
* flushing the current batch if needed to create sufficient space.
*
* See _emit_batch_header_for_composite_check_twice for a safer
* version, (but this version is fine if the safer version has
* previously been called for the same composite operation).
*/
static void
_emit_batch_header_for_composite (ScrnInfoPtr pScrn)
{
_emit_batch_header_for_composite_internal (pScrn, FALSE);
}
/* Number of buffer object in our call to check_aperture_size:
*
* batch_bo
* vertex_buffer_bo
*/
#define NUM_BO 2
static Bool
_emit_batch_header_for_composite_internal (ScrnInfoPtr pScrn, Bool check_twice)
{
ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
struct gen4_render_state *render_state= pI830->gen4_render_state;
gen4_state_t *card_state = render_state->card_state;
struct brw_surface_state_padded *ss;
gen4_composite_op *composite_op = &render_state->composite_op;
int op = composite_op->op;
PicturePtr pSrcPicture = composite_op->source_picture;
PicturePtr pMaskPicture = composite_op->mask_picture;
PicturePtr pDstPicture = composite_op->dest_picture;
PixmapPtr pSrc = composite_op->source;
PixmapPtr pMask = composite_op->mask;
PixmapPtr pDst = composite_op->dest;
uint32_t sf_state_offset;
sampler_state_filter_t src_filter, mask_filter;
sampler_state_extend_t src_extend, mask_extend;
@ -942,6 +993,33 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
int state_base_offset;
uint32_t src_blend, dst_blend;
uint32_t *binding_table;
dri_bo *bo_table[NUM_BO];
dri_bo *binding_table_bo, *surface_state_bo;
if (render_state->vertex_buffer_bo == NULL) {
render_state->vertex_buffer_bo = dri_bo_alloc (pI830->bufmgr, "vb",
sizeof (gen4_vertex_buffer),
4096);
}
bo_table[0] = pI830->batch_bo;
bo_table[1] = render_state->vertex_buffer_bo;
/* If this command won't fit in the current batch, flush. */
if (dri_bufmgr_check_aperture_space (bo_table, NUM_BO) < 0) {
intel_batch_flush (pScrn, FALSE);
if (check_twice) {
/* If the command still won't fit in an empty batch, then it's
* just plain too big for the hardware---fallback to software.
*/
if (dri_bufmgr_check_aperture_space (bo_table, NUM_BO) < 0) {
dri_bo_unreference (render_state->vertex_buffer_bo);
render_state->vertex_buffer_bo = NULL;
return FALSE;
}
}
}
IntelEmitInvarientState(pScrn);
*pI830->last_3d = LAST_3D_RENDER;
@ -984,47 +1062,52 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
i965_get_blend_cntl(op, pMaskPicture, pDstPicture->format,
&src_blend, &dst_blend);
if ((render_state->binding_table_index + 3 >=
ARRAY_SIZE(card_state->binding_table)) ||
(render_state->surface_state_index + 3 >=
ARRAY_SIZE(card_state->surface_state)))
{
i830WaitSync(pScrn);
render_state->binding_table_index = 0;
render_state->surface_state_index = 0;
render_state->vb_offset = 0;
}
binding_table = card_state->binding_table +
render_state->binding_table_index;
ss = card_state->surface_state + render_state->surface_state_index;
/* We only use 2 or 3 entries, but the table has to be 32-byte
* aligned.
*/
render_state->binding_table_index += 8;
render_state->surface_state_index += (pMask != NULL) ? 3 : 2;
/* Set up and bind the state buffer for the destination surface */
binding_table[0] = state_base_offset +
i965_set_picture_surface_state(pScrn,
&ss[0].state,
pDstPicture, pDst, TRUE);
/* Set up and bind the source surface state buffer */
binding_table[1] = state_base_offset +
i965_set_picture_surface_state(pScrn,
&ss[1].state,
pSrcPicture, pSrc, FALSE);
/* Set up the surface states. */
surface_state_bo = dri_bo_alloc (pI830->bufmgr, "surface_state",
3 * sizeof (brw_surface_state_padded),
4096);
dri_bo_map (surface_state_bo, 1);
/* Set up the state buffer for the destination surface */
i965_set_picture_surface_state(surface_state_bo, 0,
pDstPicture, pDst, TRUE);
/* Set up the source surface state buffer */
i965_set_picture_surface_state(surface_state_bo, 1,
pSrcPicture, pSrc, FALSE);
if (pMask) {
/* Set up and bind the mask surface state buffer */
binding_table[2] = state_base_offset +
i965_set_picture_surface_state(pScrn,
&ss[2].state,
pMaskPicture, pMask,
FALSE);
/* Set up the mask surface state buffer */
i965_set_picture_surface_state(surface_state_bo, 2,
pMaskPicture, pMask,
FALSE);
}
dri_bo_unmap (surface_state_bo);
/* Set up the binding table of surface indices to surface state. */
binding_table_bo = dri_bo_alloc (pI830->bufmgr, "binding_table",
3 * sizeof (uint32_t), 4096);
dri_bo_map (binding_table_bo, 1);
binding_table = binding_table_bo->virtual;
binding_table[0] = 0 * sizeof (brw_surface_state_padded) + surface_state_bo->offset;
dri_bo_emit_reloc (binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
0 * sizeof (brw_surface_state_padded),
0 * sizeof (uint32_t),
surface_state_bo);
binding_table[1] = 1 * sizeof (brw_surface_state_padded) + surface_state_bo->offset;
dri_bo_emit_reloc (binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
1 * sizeof (brw_surface_state_padded),
1 * sizeof (uint32_t),
surface_state_bo);
if (pMask) {
binding_table[2] = 2 * sizeof (brw_surface_state_padded) + surface_state_bo->offset;
dri_bo_emit_reloc (binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
2 * sizeof (brw_surface_state_padded),
2 * sizeof (uint32_t),
surface_state_bo);
} else {
binding_table[2] = 0;
}
dri_bo_unmap (binding_table_bo);
src_filter = sampler_state_filter_from_picture (pSrcPicture->filter);
if (src_filter < 0)
@ -1060,7 +1143,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(12);
/* Match Mesa driver setup */
if (IS_GM45(pI830) || IS_G4X(pI830))
if (IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
@ -1083,7 +1166,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
/* Set system instruction pointer */
OUT_BATCH(BRW_STATE_SIP | 0);
OUT_BATCH(state_base_offset + offsetof(gen4_state_t, sip_kernel));
OUT_BATCH(state_base_offset + offsetof(gen4_static_state_t, sip_kernel));
OUT_BATCH(MI_NOOP);
ADVANCE_BATCH();
}
@ -1105,8 +1188,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
assert((((unsigned char *)binding_table - pI830->FbBase) & 31) == 0);
OUT_BATCH((unsigned char *)binding_table - pI830->FbBase);
OUT_RELOC(binding_table_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
/* The drawing rectangle clipping is always on. Set it to values that
* shouldn't do any clipping.
@ -1124,17 +1206,17 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
/* Set the pointers to the 3d pipeline state */
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
assert((offsetof(gen4_state_t, vs_state) & 31) == 0);
OUT_BATCH(state_base_offset + offsetof(gen4_state_t, vs_state));
assert((offsetof(gen4_static_state_t, vs_state) & 31) == 0);
OUT_BATCH(state_base_offset + offsetof(gen4_static_state_t, vs_state));
OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
if (pMask) {
sf_state_offset = state_base_offset +
offsetof(gen4_state_t, sf_state_mask);
offsetof(gen4_static_state_t, sf_state_mask);
} else {
sf_state_offset = state_base_offset +
offsetof(gen4_state_t, sf_state);
offsetof(gen4_static_state_t, sf_state);
}
assert((sf_state_offset & 31) == 0);
OUT_BATCH(sf_state_offset);
@ -1142,7 +1224,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
/* Shorthand for long array lookup */
#define OUT_WM_KERNEL(kernel) do { \
uint32_t offset = state_base_offset + \
offsetof(gen4_state_t, \
offsetof(gen4_static_state_t, \
wm_state_ ## kernel \
[src_filter] \
[src_extend] \
@ -1182,10 +1264,10 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
#undef OUT_WM_KERNEL
/* 64 byte aligned */
assert((offsetof(gen4_state_t,
assert((offsetof(gen4_static_state_t,
cc_state[src_blend][dst_blend]) & 63) == 0);
OUT_BATCH(state_base_offset +
offsetof(gen4_state_t, cc_state[src_blend][dst_blend]));
offsetof(gen4_static_state_t, cc_state[src_blend][dst_blend]));
/* URB fence */
OUT_BATCH(BRW_URB_FENCE |
@ -1280,8 +1362,35 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
ErrorF("try to sync to show any errors...\n");
I830Sync(pScrn);
#endif
dri_bo_unreference (binding_table_bo);
dri_bo_unreference (surface_state_bo);
return TRUE;
}
#undef NUM_BO
Bool
i965_prepare_composite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture,
PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
{
ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
struct gen4_render_state *render_state= pI830->gen4_render_state;
gen4_composite_op *composite_op = &render_state->composite_op;
composite_op->op = op;
composite_op->source_picture = pSrcPicture;
composite_op->mask_picture = pMaskPicture;
composite_op->dest_picture = pDstPicture;
composite_op->source = pSrc;
composite_op->mask = pMask;
composite_op->dest = pDst;
/* Fallback if we can't make this operation fit. */
return _emit_batch_header_for_composite_check_twice (pScrn);
}
void
i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
@ -1289,13 +1398,12 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
gen4_state_t *card_state = pI830->gen4_render_state->card_state;
struct gen4_render_state *render_state = pI830->gen4_render_state;
Bool has_mask;
Bool is_affine_src, is_affine_mask, is_affine;
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
float *vb = card_state->vb;
int i;
float *vb;
is_affine_src = i830_transform_is_affine (pI830->transform[0]);
is_affine_mask = i830_transform_is_affine (pI830->transform[1]);
@ -1371,11 +1479,19 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
}
}
if (render_state->vb_offset + MAX_VERTEX_PER_COMPOSITE >= ARRAY_SIZE(card_state->vb)) {
i830WaitSync(pScrn);
/* If the vertex buffer is too full, then we flush and re-emit all
* necessary state into the batch for the composite operation. */
if (render_state->vb_offset + VERTEX_FLOATS_PER_COMPOSITE > VERTEX_BUFFER_SIZE) {
dri_bo_unreference (render_state->vertex_buffer_bo);
render_state->vertex_buffer_bo = NULL;
render_state->vb_offset = 0;
_emit_batch_header_for_composite (pScrn);
}
/* Map the vertex_buffer buffer object so we can write to it. */
dri_bo_map (render_state->vertex_buffer_bo, 1);
vb = render_state->vertex_buffer_bo->virtual;
i = render_state->vb_offset;
/* rect (x2,y2) */
vb[i++] = (float)(dstX + w);
@ -1418,7 +1534,9 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
if (!is_affine)
vb[i++] = mask_w[0];
}
assert (i * 4 <= sizeof(card_state->vb));
assert (i <= VERTEX_BUFFER_SIZE);
dri_bo_unmap (render_state->vertex_buffer_bo);
BEGIN_BATCH(12);
OUT_BATCH(MI_FLUSH);
@ -1427,7 +1545,7 @@ i965_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_BATCH((0 << VB0_BUFFER_INDEX_SHIFT) |
VB0_VERTEXDATA |
(render_state->vertex_size << VB0_BUFFER_PITCH_SHIFT));
OUT_BATCH(render_state->card_state_offset + offsetof(gen4_state_t, vb) +
OUT_RELOC(render_state->vertex_buffer_bo, I915_GEM_DOMAIN_VERTEX, 0,
render_state->vb_offset * 4);
OUT_BATCH(3);
OUT_BATCH(0); // ignore for VERTEXDATA, but still there
@ -1467,7 +1585,7 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
render_state = pI830->gen4_render_state;
render_state->card_state_offset = pI830->gen4_render_state_mem->offset;
render_state->static_state_offset = pI830->gen4_render_state_mem->offset;
if (pI830->use_drm_mode) {
ret = dri_bo_map(pI830->gen4_render_state_mem->bo, 1);
@ -1476,13 +1594,14 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
"Failed to map gen4 state\n");
return;
}
render_state->card_state = pI830->gen4_render_state_mem->bo->virtual;
render_state->static_state = pI830->gen4_render_state_mem->bo->virtual;
} else {
render_state->card_state = (gen4_state_t *)
(pI830->FbBase + render_state->card_state_offset);
render_state->static_state = (gen4_static_state_t *)
(pI830->FbBase + render_state->static_state_offset);
}
gen4_state_init(render_state);
gen4_static_state_init(render_state->static_state,
render_state->static_state_offset);
}
/**
@ -1492,16 +1611,20 @@ void
gen4_render_state_cleanup(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
struct gen4_render_state *render_state= pI830->gen4_render_state;
if (render_state->vertex_buffer_bo)
dri_bo_unreference (render_state->vertex_buffer_bo);
if (pI830->use_drm_mode) {
dri_bo_unmap(pI830->gen4_render_state_mem->bo);
dri_bo_unreference(pI830->gen4_render_state_mem->bo);
}
pI830->gen4_render_state->card_state = NULL;
render_state->static_state = NULL;
}
unsigned int
gen4_render_state_size(ScrnInfoPtr pScrn)
{
return sizeof(gen4_state_t);
return sizeof(gen4_static_state_t);
}

2
src/i965_video.c
View File

@ -584,7 +584,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
{
BEGIN_BATCH(12);
/* Match Mesa driver setup */
if (IS_GM45(pI830) || IS_G4X(pI830))
if (IS_G4X(pI830))
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
else
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);

1
src/reg_dumper/.gitignore vendored
View File

@ -1,3 +1,4 @@
intel_gtt
intel_hotplug
intel_idle
intel_reg_dumper

32
src/reg_dumper/gtt.c
View File

@ -36,22 +36,42 @@
#include "reg_dumper.h"
#include "../i810_reg.h"
#define INGTT(offset) INREG(gtt_base + (offset) / (KB(4) / 4))
#define INGTT(offset) (*(volatile uint32_t *)(gtt + (offset) / (KB(4) / 4)))
int main(int argc, char **argv)
{
I830Rec i830;
I830Ptr pI830 = &i830;
int gtt_base, start, aper_size;
int start, aper_size;
unsigned char *gtt;
intel_i830rec_init(pI830);
if (IS_G4X(pI830) || IS_GM45(pI830))
gtt_base = MB(2);
else {
if (!IS_I9XX(pI830)) {
printf("Unsupported chipset for gtt dumper\n");
exit(1);
}
aper_size = MB(256);
if (IS_G4X(pI830))
gtt = (unsigned char *)(pI830->mmio + MB(2));
else if (IS_I965G(pI830))
gtt = (unsigned char *)(pI830->mmio + KB(512));
else {
/* 915/945 chips has GTT range in bar 3*/
int err = 0;
err = pci_device_map_range (pI830->pci_dev,
pI830->pci_dev->regions[3].base_addr,
pI830->pci_dev->regions[3].size,
PCI_DEV_MAP_FLAG_WRITABLE,
(void **)&gtt);
if (err != 0) {
fprintf(stderr, "mapping GTT bar failed\n");
exit(1);
}
}
aper_size = pI830->pci_dev->regions[2].size;
for (start = 0; start < aper_size; start += KB(4)) {
uint32_t start_pte = INGTT(start);
uint32_t end;