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Cleanup gen2 tiling confusion 

A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2011-03-29 18:02:24 +02:00
parent a2c8442fcb
commit f660df2cb4
1 changed files with 3 additions and 4 deletions
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7
src/intel_uxa.c
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@ -197,13 +197,12 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
if (*tiling != I915_TILING_NONE) {
int aligned_h, tile_height;
if (*tiling == I915_TILING_X)
if (IS_GEN2(intel))
tile_height = 16;
else if (*tiling == I915_TILING_X)
tile_height = 8;
else
tile_height = 32;
/* i8xx has a 2-row interleaved tile layout */
if (IS_GEN2(intel))
tile_height *= 2;
aligned_h = ALIGN(h, tile_height);
*stride = intel_get_fence_pitch(intel,