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prime: Align pitch of shared untiled buffers to 256 bytes 

In order for nvidia to handle the buffers we are currently generating,
they need to have a pitch alignment of 256 bytes. Make it so.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2012-09-06 08:57:34 +01:00
parent c5fb025267
commit fbe4080816
2 changed files with 20 additions and 1 deletions
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5
src/intel_uxa.c
View File

@ -228,11 +228,14 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
}
if (*tiling == I915_TILING_NONE) {
/* We only require a 64 byte alignment for scanouts, but
* a 256 byte alignment for sharing with PRIME.
*/
*stride = ALIGN(pitch, 256);
/* Round the height up so that the GPU's access to a 2x2 aligned
* subspan doesn't address an invalid page offset beyond the
* end of the GTT.
*/
*stride = ALIGN(pitch, 64);
size = *stride * ALIGN(h, 2);
}

16
src/sna/sna_accel.c
View File

@ -944,6 +944,22 @@ sna_share_pixmap_backing(PixmapPtr pixmap, ScreenPtr slave, void **fd_handle)
if (priv->gpu_bo->tiling &&
!sna_pixmap_change_tiling(pixmap, I915_TILING_NONE))
return FALSE;
/* nvidia requires a minimum pitch alignment of 256 */
if (priv->gpu_bo->pitch & 255) {
struct kgem_bo *bo;
bo = kgem_replace_bo(&sna->kgem, priv->gpu_bo,
pixmap->drawable.width,
pixmap->drawable.height,
ALIGN(priv->gpu_bo->pitch, 256),
pixmap->drawable.bitsPerPixel);
if (bo == NULL)
return FALSE;
kgem_bo_destroy(&sna->kgem, priv->gpu_bo);
priv->gpu_bo = bo;
}
assert(priv->gpu_bo->tiling == I915_TILING_NONE);
/* And export the bo->pitch via pixmap->devKind */