Turns out the "new" assembler that uses mesa's opcode emission hits the
path that automatically transforms MRF registers into GRF ones in the
exa_wm_src_projective shader.
The diff with the new assembler is:
$ intel-gen4disasm -g7 -
- { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x2e8077bd, 0x008d03c0, 0x008d0180 },
mul(8) m4<1>F g30<8,8,1>F g12<8,8,1>F { align1 };
mul(8) g116<1>F g30<8,8,1>F g12<8,8,1>F { align1 };
Of course, message registers are no more in gen7, so the shader is
trying to do something shaddy (ahem!).
Instead of using m4, let's make exa_wm_src_projective use g68 for v (aka
vl) which makes sense since:
1/ vh is g69
2/ exa_wm_src_affine uses g68 for vl already
This commit changes the generated assembly, here's the decoded diff:
$ intel-gen4disasm -g7 -
- { 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 },
+ { 0x00600041, 0x288077bd, 0x008d03c0, 0x008d0180 },
mul(8) m4<1>F g30<8,8,1>F g12<8,8,1>F { align1 };
mul(8) g68<1>F g30<8,8,1>F g12<8,8,1>F { align1 };
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reported-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
These are exactly the same as the ones for Sandybridge, but with message
registers translated (hopefully) in the same way as Haihao's new
programs (m1 == g65).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Damien Lespiau
Kenneth Graunke