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Kenneth Graunke 07cc488bcf render: New Ivybridge assembly programs for render acceleration. 
These are exactly the same as the ones for Sandybridge, but with message
registers translated (hopefully) in the same way as Haihao's new
programs (m1 == g65).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
 		2011-07-28 15:00:17 -07:00
..
legacy Don't include xf86Priv.h 2011-06-22 22:39:37 +01:00
render_program render: New Ivybridge assembly programs for render acceleration. 2011-07-28 15:00:17 -07:00
scripts Review PLL spreadsheet and update register ranges. 2007-11-13 22:28:22 -08:00
sna sna: Revert enabling scan-line wait on SNB 2011-07-26 08:29:36 +01:00
xvmc Fix IGD and IGDNG constants to be comprehensible 2011-02-17 20:36:45 +00:00
Makefile.am sna: Introduce a new acceleration model. 2011-06-04 09:19:46 +01:00
brw_defines.h Document and use 'legacy' border color mode 2008-10-06 13:22:08 -07:00
brw_structs.h Xv: update SURFACE_STATE & SAMPLER_STATE for Xv on Ivybridge 2011-06-24 09:42:13 +08:00
common.h Move EDID_COMPLETE_RAWDATA define to intel.h to avoid redifinition warning 2010-10-13 09:51:57 +01:00
i830_3d.c Rename common infrastructure to the intel namespace. 2010-06-25 13:18:01 +01:00
i830_reg.h add BLT ring support 2010-11-01 10:37:51 +00:00
i830_render.c i830: amalgamate consecutive composites into a single primitive 2010-12-23 19:42:19 +00:00
i915_3d.c Rename common infrastructure to the intel namespace. 2010-06-25 13:18:01 +01:00
i915_3d.h Revert "xp:trapezoids" 2010-06-09 10:03:29 +01:00
i915_reg.h i915: Move vertices into a vertex buffer object. 2010-05-24 09:36:23 +01:00
i915_render.c i965: Avoid transform overheads for vertex emit where possible 2011-04-07 15:09:21 +01:00
i915_video.c i915/video: Clip indirect Xv output 2011-03-16 08:40:08 +00:00
i965_reg.h Xv: set up pipeline for Xv on Ivybridge 2011-06-24 09:42:19 +08:00
i965_render.c render: New Ivybridge assembly programs for render acceleration. 2011-07-28 15:00:17 -07:00
i965_video.c Xv: set up pipeline for Xv on Ivybridge 2011-06-24 09:42:19 +08:00
intel.h dri: Enable triple-bufferred pageflips 2011-07-11 22:13:01 +01:00
intel_batchbuffer.c Add support for Ivybridge chipset. 2011-05-09 22:56:42 -07:00
intel_batchbuffer.h Ensure that the partial batch is flushed upon the blockhandler 2011-05-07 20:04:18 +01:00
intel_display.c Disable adding normal RTF modes for an eDP 2011-07-13 21:11:14 +01:00
intel_dri.c dri: Do not tile stencil buffer 2011-07-19 13:08:18 -07:00
intel_driver.c dri: Enable triple-bufferred pageflips 2011-07-11 22:13:01 +01:00
intel_driver.h Add support for Ivybridge chipset. 2011-05-09 22:56:42 -07:00
intel_hwmc.c Include a chipset generation number to clarify device specific paths. 2010-10-07 13:26:07 +01:00
intel_hwmc.h Rename common infrastructure to the intel namespace. 2010-06-25 13:18:01 +01:00
intel_memory.c Turn relaxed-fencing off by default for older (pre-G33) chipsets 2011-04-12 09:03:01 +01:00
intel_module.c sna: Distinguish 830/845 vs 855/865 using the generation id 2011-06-30 16:31:28 +01:00
intel_shadow.c Disable BLT for i830 and 845G 2010-11-23 22:29:52 +00:00
intel_uxa.c intel: Restore manual flush for old kernels 2011-04-08 13:38:48 +01:00
intel_video.c video: Flush the batch on the next blockhandler after queuing 2011-05-10 20:36:18 +01:00
intel_video.h Xv: setup pipeline for Xv on Sandybridge 2010-11-01 08:51:13 +08:00