75 lines
2.5 KiB
Plaintext
75 lines
2.5 KiB
Plaintext
/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Wang Zhenyu <zhenyu.z.wang@intel.com>
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* Keith Packard <keithp@keithp.com>
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*/
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include(`exa_wm.g4i')
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/*
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* Prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2),
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*
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* Note that the SIMD16 write message takes data for the first
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* two sub-spans followed by the data for the second two sub-spans
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* instead of having the two sub-spans interleaved by channel. Weird.
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*/
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mov (8) data_port_r_01<1>F src_sample_r_01<8,8,1>F { align1 };
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mov (8) data_port_g_01<1>F src_sample_g_01<8,8,1>F { align1 };
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mov (8) data_port_b_01<1>F src_sample_b_01<8,8,1>F { align1 };
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mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 };
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mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { sechalf align1 };
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mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { sechalf align1 };
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mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { sechalf align1 };
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mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { sechalf align1 };
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/* m0, m1 are all direct passed by PS thread payload */
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mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { mask_disable align1 };
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/* write */
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send (16)
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data_port_msg_0_ind
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acc0<1>UW
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g0<8,8,1>UW
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write (
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0, /* binding_table */
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8, /* pixel scordboard clear, msg type simd16 single source */
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4, /* render target write */
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0 /* no write commit message */
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)
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mlen 10
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rlen 0
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{ align1 EOT };
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nop;
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nop;
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nop;
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nop;
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nop;
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nop;
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nop;
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nop;
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