125 lines
4.7 KiB
C
125 lines
4.7 KiB
C
/**************************************************************************
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Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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*/
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/*
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* XXX So far, for GXxor this is about 40% of the speed of SW, but CPU
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* utilisation falls from 95% to < 5%.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "xf86.h"
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#include "i830.h"
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#include "i810_reg.h"
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#include "i915_drm.h"
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unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap)
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{
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return (unsigned long)pixmap->devKind;
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}
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void i830_debug_flush(ScrnInfoPtr scrn)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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if (intel->debug_flush & DEBUG_FLUSH_CACHES)
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intel_batch_emit_flush(scrn);
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if (intel->debug_flush & DEBUG_FLUSH_BATCHES)
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intel_batch_submit(scrn);
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}
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/* The following function sets up the supported acceleration. Call it
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* from the FbInit() function in the SVGA driver, or before ScreenInit
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* in a monolithic server.
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*/
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Bool I830AccelInit(ScreenPtr screen)
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{
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ScrnInfoPtr scrn = xf86Screens[screen->myNum];
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intel_screen_private *intel = intel_get_screen_private(scrn);
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/* Limits are described in the BLT engine chapter under Graphics Data Size
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* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
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* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
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*
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* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
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*
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* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
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* i965 limits 3D surface to 4kB-aligned offset if tiled.
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* i965 limits 3D surfaces to w,h of ?,8192.
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* i965 limits 3D surface to pitch of 1B - 128kB.
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* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
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* i965 limits 3D surface pitch alignment to 512B if tiled.
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* i965 limits 3D destination drawing rect to w,h of 8192,8192.
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*
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* i915 limits 3D textures to 4B-aligned offset if un-tiled.
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* i915 limits 3D textures to ~4kB-aligned offset if tiled.
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* i915 limits 3D textures to width,height of 2048,2048.
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* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
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* i915 limits 3D destination to ~4kB-aligned offset if tiled.
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* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
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* i915 limits 3D destination to pitch 64B-aligned if used with depth.
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* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
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* i915 limits 3D destination to POT aligned pitch if tiled.
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* i915 limits 3D destination drawing rect to w,h of 2048,2048.
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*
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* i845 limits 3D textures to 4B-aligned offset if un-tiled.
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* i845 limits 3D textures to ~4kB-aligned offset if tiled.
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* i845 limits 3D textures to width,height of 2048,2048.
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* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
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* i845 limits 3D destination to 4B-aligned offset if un-tiled.
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* i845 limits 3D destination to ~4kB-aligned offset if tiled.
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* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
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* i845 limits 3D destination drawing rect to w,h of 2048,2048.
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*
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* For the tiled issues, the only tiled buffer we draw to should be
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* the front, which will have an appropriate pitch/offset already set up,
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* so UXA doesn't need to worry.
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*/
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if (IS_I965G(intel)) {
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intel->accel_pixmap_offset_alignment = 4 * 2;
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intel->accel_pixmap_pitch_alignment = 64;
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intel->accel_max_x = 8192;
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intel->accel_max_y = 8192;
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} else {
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intel->accel_pixmap_offset_alignment = 4;
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intel->accel_pixmap_pitch_alignment = 64;
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intel->accel_max_x = 2048;
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intel->accel_max_y = 2048;
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}
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return i830_uxa_init(screen);
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}
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