241 lines
7.3 KiB
C
241 lines
7.3 KiB
C
/**************************************************************************
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Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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*/
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/*
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* XXX So far, for GXxor this is about 40% of the speed of SW, but CPU
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* utilisation falls from 95% to < 5%.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <errno.h>
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#include "xf86.h"
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#include "i830.h"
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#include "i810_reg.h"
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#include "i830_debug.h"
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#include "i830_ring.h"
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#include "i915_drm.h"
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unsigned long
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intel_get_pixmap_offset(PixmapPtr pPix)
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{
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ScreenPtr pScreen = pPix->drawable.pScreen;
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ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
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I830Ptr pI830 = I830PTR(pScrn);
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return (unsigned long)pPix->devPrivate.ptr - (unsigned long)pI830->FbBase;
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}
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unsigned long
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intel_get_pixmap_pitch(PixmapPtr pPix)
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{
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return (unsigned long)pPix->devKind;
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}
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int
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I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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I830RingBuffer *ring = &pI830->ring;
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int iters = 0;
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unsigned int start = 0;
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unsigned int now = 0;
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int last_head = 0;
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unsigned int first = 0;
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/* If your system hasn't moved the head pointer in 2 seconds, I'm going to
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* call it crashed.
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*/
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if (timeout_millis == 0)
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timeout_millis = 2000;
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if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {
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ErrorF("I830WaitLpRing %d\n", n);
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first = GetTimeInMillis();
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}
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while (ring->space < n) {
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ring->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->mem->size;
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iters++;
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now = GetTimeInMillis();
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if (start == 0 || now < start || ring->head != last_head) {
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if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
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if (now > start)
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ErrorF("space: %d wanted %d\n", ring->space, n);
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start = now;
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last_head = ring->head;
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} else if (now - start > timeout_millis) {
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ErrorF("Error in I830WaitLpRing(), timeout for %d seconds\n",
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timeout_millis/1000);
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if (IS_I965G(pI830))
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i965_dump_error_state(pScrn);
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else
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i830_dump_error_state(pScrn);
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ErrorF("space: %d wanted %d\n", ring->space, n);
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pI830->uxa_driver = NULL;
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FatalError("lockup\n");
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}
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DELAY(10);
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}
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if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {
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now = GetTimeInMillis();
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if (now - first) {
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ErrorF("Elapsed %u ms\n", now - first);
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ErrorF("space: %d wanted %d\n", ring->space, n);
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}
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}
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return iters;
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}
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void
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I830Sync(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
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ErrorF("I830Sync\n");
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if (!pScrn->vtSema || !pI830->batch_bo)
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return;
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I830EmitFlush(pScrn);
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intel_batch_flush(pScrn, TRUE);
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intel_batch_wait_last(pScrn);
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}
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void
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I830EmitFlush(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
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if (IS_I965G(pI830))
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flags = 0;
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{
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BEGIN_BATCH(1);
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OUT_BATCH(MI_FLUSH | flags);
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ADVANCE_BATCH();
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}
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}
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#if (ALWAYS_SYNC || ALWAYS_FLUSH)
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void
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i830_debug_sync(ScrnInfoPtr scrn)
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{
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if (ALWAYS_SYNC)
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I830Sync(scrn);
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else
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intel_batch_flush(scrn, FALSE);
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}
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#endif
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/* The following function sets up the supported acceleration. Call it
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* from the FbInit() function in the SVGA driver, or before ScreenInit
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* in a monolithic server.
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*/
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Bool
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I830AccelInit(ScreenPtr pScreen)
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{
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ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
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I830Ptr pI830 = I830PTR(pScrn);
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/* Limits are described in the BLT engine chapter under Graphics Data Size
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* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
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* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
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*
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* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
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*
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* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
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* i965 limits 3D surface to 4kB-aligned offset if tiled.
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* i965 limits 3D surfaces to w,h of ?,8192.
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* i965 limits 3D surface to pitch of 1B - 128kB.
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* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
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* i965 limits 3D surface pitch alignment to 512B if tiled.
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* i965 limits 3D destination drawing rect to w,h of 8192,8192.
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*
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* i915 limits 3D textures to 4B-aligned offset if un-tiled.
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* i915 limits 3D textures to ~4kB-aligned offset if tiled.
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* i915 limits 3D textures to width,height of 2048,2048.
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* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
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* i915 limits 3D destination to ~4kB-aligned offset if tiled.
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* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
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* i915 limits 3D destination to pitch 64B-aligned if used with depth.
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* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
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* i915 limits 3D destination to POT aligned pitch if tiled.
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* i915 limits 3D destination drawing rect to w,h of 2048,2048.
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*
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* i845 limits 3D textures to 4B-aligned offset if un-tiled.
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* i845 limits 3D textures to ~4kB-aligned offset if tiled.
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* i845 limits 3D textures to width,height of 2048,2048.
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* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
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* i845 limits 3D destination to 4B-aligned offset if un-tiled.
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* i845 limits 3D destination to ~4kB-aligned offset if tiled.
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* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
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* i845 limits 3D destination drawing rect to w,h of 2048,2048.
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*
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* For the tiled issues, the only tiled buffer we draw to should be
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* the front, which will have an appropriate pitch/offset already set up,
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* so UXA doesn't need to worry.
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*/
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if (IS_I965G(pI830)) {
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pI830->accel_pixmap_offset_alignment = 4 * 2;
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pI830->accel_pixmap_pitch_alignment = 64;
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pI830->accel_max_x = 8192;
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pI830->accel_max_y = 8192;
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} else {
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pI830->accel_pixmap_offset_alignment = 4;
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pI830->accel_pixmap_pitch_alignment = 64;
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pI830->accel_max_x = 2048;
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pI830->accel_max_y = 2048;
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}
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/* Bump the pitch so that we can tile any pixmap we create. */
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if (pI830->directRenderingType >= DRI_DRI2)
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pI830->accel_pixmap_pitch_alignment = 512;
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return i830_uxa_init(pScreen);
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}
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