242 lines
6.3 KiB
C
242 lines
6.3 KiB
C
/* -*- c-basic-offset: 4 -*- */
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/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <assert.h>
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#include <stdlib.h>
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#include <errno.h>
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#include "xf86.h"
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#include "i830.h"
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#include "i830_ring.h"
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#include "i915_drm.h"
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static int
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intel_nondrm_exec(dri_bo *bo, unsigned int used, void *priv)
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{
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ScrnInfoPtr pScrn = priv;
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I830Ptr pI830 = I830PTR(pScrn);
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BEGIN_LP_RING(4);
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OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
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OUT_RING(bo->offset);
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OUT_RING(MI_NOOP);
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OUT_RING(MI_NOOP);
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ADVANCE_LP_RING();
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return 0;
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}
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static int
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intel_nondrm_exec_i830(dri_bo *bo, unsigned int used, void *priv)
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{
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ScrnInfoPtr pScrn = priv;
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I830Ptr pI830 = I830PTR(pScrn);
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BEGIN_LP_RING(4);
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OUT_RING(MI_BATCH_BUFFER);
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OUT_RING(bo->offset);
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OUT_RING(bo->offset + pI830->batch_used - 4);
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OUT_RING(MI_NOOP);
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ADVANCE_LP_RING();
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return 0;
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}
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/**
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* Creates a fence value representing a request to be passed.
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*
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* Stub implementation that should be avoided when DRM functions are available.
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*/
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static unsigned int
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intel_nondrm_emit(void *priv)
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{
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static unsigned int fence = 0;
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/* Match DRM in not using half the range. The fake bufmgr relies on this. */
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if (++fence >= 0x8000000)
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fence = 1;
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return fence;
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}
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/**
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* Waits on a fence representing a request to be passed.
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*
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* Stub implementation that should be avoided when DRM functions are available.
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*/
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static void
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intel_nondrm_wait(unsigned int fence, void *priv)
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{
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ScrnInfoPtr pScrn = priv;
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i830_wait_ring_idle(pScrn);
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}
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static void
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intel_next_batch(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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/* The 865 has issues with larger-than-page-sized batch buffers. */
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if (IS_I865G(pI830))
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pI830->batch_bo = dri_bo_alloc(pI830->bufmgr, "batch", 4096, 4096);
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else
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pI830->batch_bo = dri_bo_alloc(pI830->bufmgr, "batch", 4096 * 4, 4096);
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if (dri_bo_map(pI830->batch_bo, 1) != 0)
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FatalError("Failed to map batchbuffer: %s\n", strerror(errno));
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pI830->batch_used = 0;
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pI830->batch_ptr = pI830->batch_bo->virtual;
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/* If we are using DRI2, we don't know when another client has executed,
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* so we have to reinitialize our 3D state per batch.
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*/
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if (pI830->directRenderingType == DRI_DRI2)
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pI830->last_3d = LAST_3D_OTHER;
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}
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void
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intel_batch_init(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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pI830->batch_emit_start = 0;
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pI830->batch_emitting = 0;
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intel_next_batch(pScrn);
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if (pI830->directRenderingType <= DRI_NONE) {
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if (IS_I830(pI830) || IS_845G(pI830)) {
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intel_bufmgr_fake_set_exec_callback(pI830->bufmgr,
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intel_nondrm_exec_i830,
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pScrn);
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} else {
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intel_bufmgr_fake_set_exec_callback(pI830->bufmgr,
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intel_nondrm_exec,
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pScrn);
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}
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intel_bufmgr_fake_set_fence_callback(pI830->bufmgr,
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intel_nondrm_emit,
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intel_nondrm_wait,
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pScrn);
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}
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}
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void
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intel_batch_teardown(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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if (pI830->batch_ptr != NULL) {
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dri_bo_unmap(pI830->batch_bo);
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pI830->batch_ptr = NULL;
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dri_bo_unreference(pI830->batch_bo);
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pI830->batch_bo = NULL;
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dri_bo_unreference(pI830->last_batch_bo);
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pI830->last_batch_bo = NULL;
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}
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}
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void
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intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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int ret;
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if (pI830->batch_used == 0)
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return;
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/* If we're not using GEM, then emit a flush after each batch buffer */
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if (pI830->memory_manager == NULL && !flushed) {
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int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
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if (IS_I965G(pI830))
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flags = 0;
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*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_FLUSH | flags;
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pI830->batch_used += 4;
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}
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/* Emit a padding dword if we aren't going to be quad-word aligned. */
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if ((pI830->batch_used & 4) == 0) {
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*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
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pI830->batch_used += 4;
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}
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/* Mark the end of the batchbuffer. */
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*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_BATCH_BUFFER_END;
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pI830->batch_used += 4;
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dri_bo_unmap(pI830->batch_bo);
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pI830->batch_ptr = NULL;
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ret = dri_bo_exec(pI830->batch_bo, pI830->batch_used, NULL, 0, 0xffffffff);
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if (ret != 0)
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FatalError("Failed to submit batchbuffer: %s\n", strerror(-ret));
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/* Save a ref to the last batch emitted, which we use for syncing
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* in debug code.
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*/
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dri_bo_unreference(pI830->last_batch_bo);
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pI830->last_batch_bo = pI830->batch_bo;
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pI830->batch_bo = NULL;
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intel_next_batch(pScrn);
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/* Mark that we need to flush whatever potential rendering we've done in the
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* blockhandler. We could set this less often, but it's probably not worth
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* the work.
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*/
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if (pI830->memory_manager != NULL)
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pI830->need_mi_flush = TRUE;
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if (pI830->batch_flush_notify)
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pI830->batch_flush_notify (pScrn);
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}
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/** Waits on the last emitted batchbuffer to be completed. */
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void
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intel_batch_wait_last(ScrnInfoPtr scrn)
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{
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I830Ptr pI830 = I830PTR(scrn);
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/* Map it CPU write, which guarantees it's done. This is a completely
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* non performance path, so we don't need anything better.
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*/
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drm_intel_bo_map(pI830->last_batch_bo, TRUE);
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drm_intel_bo_unmap(pI830->last_batch_bo);
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}
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