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sna: Fix alignment of the base of partial buffers for pre-G33 chipsets 

The older chipsets have much more restrictive alignment rules for the
base address of tiled but unfenced objects.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1120108
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2013-02-09 15:30:58 +00:00
parent 80044e5463
commit 42a6b25817
1 changed files with 3 additions and 0 deletions
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3
src/sna/sna_render.c
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@ -899,6 +899,9 @@ sna_render_pixmap_partial(struct sna *sna,
DBG(("%s: tile size for tiling %d: %dx%d, size=%d\n",
__FUNCTION__, bo->tiling, tile_width, tile_height, tile_size));
if (sna->kgem.gen < 033)
tile_width = bo->pitch;
/* Ensure we align to an even tile row */
box.y1 = box.y1 & ~(2*tile_height - 1);
box.y2 = ALIGN(box.y2, 2*tile_height);