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sna/gen5: Force a MI_FLUSH between using the BLT and RENDER engines 

There is a workaround that says the first RENDER command following use of
the BLT should be a non-pipelined command. To be safe, emit a MI_FLUSH
before setting up the invariants.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1168066
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2013-04-12 10:23:43 +01:00
parent aff14a23f9
commit 97fc1d4c5b
1 changed files with 6 additions and 1 deletions
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7
src/sna/gen5_render.c
View File

@ -756,8 +756,13 @@ gen5_emit_invariant(struct sna *sna)
*
* However, the kernel flushes the pipeline between batches,
* so we should be safe....
* OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
*
* On the other hand, after using BLT we must use a non-pipelined
* operation...
*/
if (sna->kgem.nreloc)
OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen5_emit_state_base_address(sna);