Move i965 video surface state and binding table to BOs.
This commit is contained in:
Eric Anholt
parent
1b3c3c9d79
commit
ae2cd8b75e
137
src/i965_video.c
137
src/i965_video.c
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@ -343,12 +343,19 @@ intel_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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return target_bo->offset + target_offset;
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}
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static void
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i965_set_dst_surface_state(ScrnInfoPtr scrn,
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struct brw_surface_state *dest_surf_state,
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PixmapPtr pixmap)
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static drm_intel_bo *
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i965_create_dst_surface_state(ScrnInfoPtr scrn,
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PixmapPtr pixmap)
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{
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I830Ptr pI830 = I830PTR(scrn);
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struct brw_surface_state *dest_surf_state;
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drm_intel_bo *surf_bo;
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surf_bo = drm_intel_bo_alloc(pI830->bufmgr,
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"textured video surface state",
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4096, 4096);
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drm_intel_bo_map(surf_bo, TRUE);
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dest_surf_state = surf_bo->virtual;
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memset(dest_surf_state, 0, sizeof(*dest_surf_state));
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dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
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@ -376,17 +383,29 @@ i965_set_dst_surface_state(ScrnInfoPtr scrn,
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dest_surf_state->ss3.pitch = intel_get_pixmap_pitch(pixmap) - 1;
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dest_surf_state->ss3.tiled_surface = i830_pixmap_tiled(pixmap);
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dest_surf_state->ss3.tile_walk = 0; /* TileX */
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drm_intel_bo_unmap(surf_bo);
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return surf_bo;
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}
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static void
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i965_set_src_surface_state(ScrnInfoPtr scrn,
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struct brw_surface_state *src_surf_state,
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static drm_intel_bo *
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i965_create_src_surface_state(ScrnInfoPtr scrn,
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uint32_t src_offset,
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int src_width,
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int src_height,
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int src_pitch,
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uint32_t src_surf_format)
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{
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I830Ptr pI830 = I830PTR(scrn);
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drm_intel_bo *surface_bo;
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struct brw_surface_state *src_surf_state;
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surface_bo = drm_intel_bo_alloc(pI830->bufmgr,
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"textured video surface state",
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4096, 4096);
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drm_intel_bo_map(surface_bo, TRUE);
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src_surf_state = surface_bo->virtual;
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/* Set up the source surface state buffer */
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memset(src_surf_state, 0, sizeof(struct brw_surface_state));
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src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
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@ -407,6 +426,34 @@ i965_set_src_surface_state(ScrnInfoPtr scrn,
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src_surf_state->ss2.mip_count = 0;
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src_surf_state->ss2.render_target_rotation = 0;
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src_surf_state->ss3.pitch = src_pitch - 1;
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drm_intel_bo_unmap(surface_bo);
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return surface_bo;
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}
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static drm_intel_bo *
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i965_create_binding_table(ScrnInfoPtr scrn, drm_intel_bo **surf_bos, int n_surf)
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{
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I830Ptr pI830 = I830PTR(scrn);
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drm_intel_bo *bind_bo;
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uint32_t *binding_table;
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int i;
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/* Set up a binding table for our surfaces. Only the PS will use it */
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bind_bo = drm_intel_bo_alloc(pI830->bufmgr,
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"textured video binding table",
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4096, 4096);
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drm_intel_bo_map(bind_bo, TRUE);
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binding_table = bind_bo->virtual;
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for (i = 0; i < n_surf; i++)
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binding_table[i] = intel_emit_reloc(bind_bo, i * sizeof(uint32_t),
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surf_bos[i], 0,
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I915_GEM_DOMAIN_INSTRUCTION, 0);
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drm_intel_bo_unmap(bind_bo);
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return bind_bo;
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}
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static drm_intel_bo *
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@ -662,20 +709,14 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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int urb_sf_start, urb_sf_size;
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int urb_cs_start, urb_cs_size;
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float src_scale_x, src_scale_y;
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uint32_t *binding_table;
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int dest_surf_offset, src_surf_offset[6];
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int binding_table_offset;
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int next_offset, total_state_size;
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char *state_base;
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int state_base_offset;
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int src_surf;
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int src_surf, i;
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int n_src_surf;
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uint32_t src_surf_format;
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uint32_t src_surf_base[6];
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int src_width[6];
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int src_height[6];
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int src_pitch[6];
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int wm_binding_table_entries;
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drm_intel_bo *bind_bo, *surf_bos[7];
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#if 0
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ErrorF("BroadwaterDisplayVideoTextured: %dx%d (pitch %d)\n", width, height,
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@ -733,44 +774,13 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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default:
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return;
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}
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wm_binding_table_entries = 1 + n_src_surf;
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IntelEmitInvarientState(pScrn);
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*pI830->last_3d = LAST_3D_VIDEO;
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next_offset = 0;
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/* Set up our layout of state in framebuffer: */
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/* And then the general state: */
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dest_surf_offset = ALIGN(next_offset, 32);
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next_offset = dest_surf_offset + sizeof(struct brw_surface_state);
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for (src_surf = 0; src_surf < n_src_surf; src_surf++) {
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src_surf_offset[src_surf] = ALIGN(next_offset, 32);
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next_offset = src_surf_offset[src_surf] + sizeof(struct brw_surface_state);
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}
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binding_table_offset = ALIGN(next_offset, 32);
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next_offset = binding_table_offset + (wm_binding_table_entries * 4);
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/* Allocate an area in framebuffer for our state layout we just set up */
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total_state_size = next_offset;
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assert (total_state_size < BRW_LINEAR_EXTRA);
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/*
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* Use the extra space allocated at the end of the Xv buffer
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*/
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state_base_offset = pPriv->extra_offset;
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state_base_offset = ALIGN(state_base_offset, 64);
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state_base = (char *)(pI830->FbBase + state_base_offset);
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binding_table = (void *)(state_base + binding_table_offset);
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#if 0
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ErrorF("dst surf: 0x%08x\n", state_base_offset + dest_surf_offset);
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ErrorF("src surf: 0x%08x\n", state_base_offset + src_surf_offset);
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ErrorF("binding table: 0x%08x\n", state_base_offset + binding_table_offset);
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#endif
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urb_vs_start = 0;
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@ -790,24 +800,22 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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*/
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/* Upload kernels */
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i965_set_dst_surface_state(pScrn, (void *)(state_base +
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dest_surf_offset),
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pPixmap);
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surf_bos[0] = i965_create_dst_surface_state(pScrn, pPixmap);
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for (src_surf = 0; src_surf < n_src_surf; src_surf++)
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i965_set_src_surface_state(pScrn,
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(void *)(state_base +
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src_surf_offset[src_surf]),
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src_surf_base[src_surf],
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src_width[src_surf],
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src_height[src_surf],
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src_pitch[src_surf],
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src_surf_format);
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/* Set up a binding table for our surfaces. Only the PS will use it */
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binding_table[0] = state_base_offset + dest_surf_offset;
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for (src_surf = 0; src_surf < n_src_surf; src_surf++)
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binding_table[1 + src_surf] = state_base_offset + src_surf_offset[src_surf];
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for (src_surf = 0; src_surf < n_src_surf; src_surf++) {
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surf_bos[src_surf + 1] =
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i965_create_src_surface_state(pScrn,
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src_surf_base[src_surf],
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src_width[src_surf],
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src_height[src_surf],
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src_pitch[src_surf],
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src_surf_format);
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}
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bind_bo = i965_create_binding_table(pScrn, surf_bos, n_src_surf + 1);
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for (i = 0; i < n_src_surf + 1; i++) {
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drm_intel_bo_unreference(surf_bos[i]);
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surf_bos[i] = NULL;
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}
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if (pI830->video.gen4_sampler_bo == NULL)
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pI830->video.gen4_sampler_bo = i965_create_sampler_state(pScrn);
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@ -900,7 +908,8 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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OUT_BATCH(0); /* clip */
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OUT_BATCH(0); /* sf */
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/* Only the PS uses the binding table */
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OUT_BATCH(state_base_offset + binding_table_offset); /* ps */
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OUT_RELOC(bind_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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drm_intel_bo_unreference(bind_bo);
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/* Blend constant color (magenta is fun) */
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OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
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