Move i965 render kernels to BOs.
This commit is contained in:
Eric Anholt
parent
5d705de5d1
commit
befd4ad8be
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@ -390,12 +390,6 @@ static const uint32_t ps_kernel_masknoca_projective_static [][4] = {
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#include "exa_wm_write.g4b"
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};
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/**
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* Storage for the static kernel data with template name, rounded to 64 bytes.
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*/
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#define KERNEL_DECL(template) \
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uint32_t template [((sizeof (template ## _static) + 63) & ~63) / 16][4];
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#define WM_STATE_DECL(kernel) \
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struct brw_wm_unit_state wm_state_ ## kernel[SAMPLER_STATE_FILTER_COUNT] \
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[SAMPLER_STATE_EXTEND_COUNT] \
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@ -484,18 +478,6 @@ struct gen4_cc_unit_state {
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* state that we use for Render acceleration.
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*/
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typedef struct _gen4_static_state {
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KERNEL_DECL (sip_kernel);
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KERNEL_DECL (sf_kernel);
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KERNEL_DECL (sf_kernel_mask);
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KERNEL_DECL (ps_kernel_nomask_affine);
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KERNEL_DECL (ps_kernel_nomask_projective);
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KERNEL_DECL (ps_kernel_maskca_affine);
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KERNEL_DECL (ps_kernel_maskca_projective);
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KERNEL_DECL (ps_kernel_maskca_srcalpha_affine);
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KERNEL_DECL (ps_kernel_maskca_srcalpha_projective);
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KERNEL_DECL (ps_kernel_masknoca_affine);
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KERNEL_DECL (ps_kernel_masknoca_projective);
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/* Index by [src_filter][src_extend][mask_filter][mask_extend]. Two of
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* the structs happen to add to 32 bytes.
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*/
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@ -542,6 +524,7 @@ struct gen4_render_state {
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[SAMPLER_STATE_EXTEND_COUNT];
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drm_intel_bo *wm_kernel_bo[WM_KERNEL_COUNT];
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drm_intel_bo *sip_kernel_bo;
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dri_bo* vertex_buffer_bo;
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gen4_composite_op composite_op;
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@ -560,7 +543,7 @@ struct gen4_render_state {
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* back to SF which then hands pixels off to WM.
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*/
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static drm_intel_bo *
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gen4_create_sf_state(ScrnInfoPtr scrn, int kernel_offset)
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gen4_create_sf_state(ScrnInfoPtr scrn, drm_intel_bo *kernel_bo)
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{
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I830Ptr pI830 = I830PTR(scrn);
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struct brw_sf_unit_state *sf_state;
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@ -573,6 +556,11 @@ gen4_create_sf_state(ScrnInfoPtr scrn, int kernel_offset)
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memset(sf_state, 0, sizeof(*sf_state));
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sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
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sf_state->thread0.kernel_start_pointer =
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intel_emit_reloc(sf_state_bo,
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offsetof(struct brw_sf_unit_state, thread0),
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kernel_bo, sf_state->thread0.grf_reg_count << 1,
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I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6;
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sf_state->sf1.single_program_flow = 1;
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sf_state->sf1.binding_table_entry_count = 0;
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sf_state->sf1.thread_priority = 0;
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@ -600,9 +588,6 @@ gen4_create_sf_state(ScrnInfoPtr scrn, int kernel_offset)
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sf_state->sf6.dest_org_vbias = 0x8;
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sf_state->sf6.dest_org_hbias = 0x8;
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assert((kernel_offset & 63) == 0);
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sf_state->thread0.kernel_start_pointer = kernel_offset >> 6;
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drm_intel_bo_unmap(sf_state_bo);
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return sf_state_bo;
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@ -847,14 +832,6 @@ gen4_static_state_init (gen4_static_state_t *static_state,
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{
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int i, j, k, l;
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#define KERNEL_COPY(kernel) \
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memcpy(static_state->kernel, kernel ## _static, sizeof(kernel ## _static))
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KERNEL_COPY (sip_kernel);
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KERNEL_COPY (sf_kernel);
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KERNEL_COPY (sf_kernel_mask);
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#undef KERNEL_COPY
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/* Set up the sampler border color (always transparent black) */
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memset(&static_state->sampler_border_color, 0,
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sizeof(static_state->sampler_border_color));
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@ -1024,8 +1001,6 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
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int urb_clip_start, urb_clip_size;
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int urb_sf_start, urb_sf_size;
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int urb_cs_start, urb_cs_size;
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char *state_base;
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int state_base_offset;
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uint32_t src_blend, dst_blend;
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dri_bo *binding_table_bo = composite_op->binding_table_bo;
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wm_kernel_t wm_kernel;
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@ -1035,10 +1010,6 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
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IntelEmitInvarientState(pScrn);
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*pI830->last_3d = LAST_3D_RENDER;
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state_base_offset = pI830->gen4_render_state_mem->offset;
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assert((state_base_offset & 63) == 0);
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state_base = (char *)(pI830->FbBase + state_base_offset);
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urb_vs_start = 0;
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urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
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urb_gs_start = urb_vs_start + urb_vs_size;
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@ -1091,7 +1062,8 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
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/* Set system instruction pointer */
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OUT_BATCH(BRW_STATE_SIP | 0);
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OUT_BATCH(state_base_offset + offsetof(gen4_static_state_t, sip_kernel));
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OUT_RELOC(render_state->sip_kernel_bo,
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I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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}
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@ -1651,6 +1623,7 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
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uint32_t static_state_offset;
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int ret;
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int i, j, k, l, m;
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drm_intel_bo *sf_kernel_bo, *sf_kernel_mask_bo;
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if (pI830->gen4_render_state == NULL)
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pI830->gen4_render_state = calloc(sizeof(*render_state), 1);
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@ -1676,15 +1649,21 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
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render_state->static_state_offset);
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render_state->vs_state_bo = gen4_create_vs_unit_state(pScrn);
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/* Set up the two SF states (one for blending with a mask, one without) */
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render_state->sf_state_bo =
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gen4_create_sf_state(pScrn, static_state_offset +
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offsetof(gen4_static_state_t,
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sf_kernel));
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render_state->sf_mask_state_bo =
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gen4_create_sf_state(pScrn, static_state_offset +
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offsetof(gen4_static_state_t,
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sf_kernel_mask));
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sf_kernel_bo = intel_bo_alloc_for_data(pScrn,
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sf_kernel_static,
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sizeof(sf_kernel_static),
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"sf kernel");
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sf_kernel_mask_bo = intel_bo_alloc_for_data(pScrn,
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sf_kernel_mask_static,
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sizeof(sf_kernel_mask_static),
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"sf mask kernel");
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render_state->sf_state_bo = gen4_create_sf_state(pScrn, sf_kernel_bo);
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render_state->sf_mask_state_bo = gen4_create_sf_state(pScrn,
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sf_kernel_mask_bo);
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drm_intel_bo_unreference(sf_kernel_bo);
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drm_intel_bo_unreference(sf_kernel_mask_bo);
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for (m = 0; m < WM_KERNEL_COUNT; m++) {
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render_state->wm_kernel_bo[m] =
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@ -1717,6 +1696,10 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
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}
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render_state->cc_state_bo = gen4_create_cc_unit_state(pScrn);
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render_state->sip_kernel_bo = intel_bo_alloc_for_data(pScrn,
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sip_kernel_static,
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sizeof(sip_kernel_static),
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"sip kernel");
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}
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/**
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@ -1751,6 +1734,8 @@ gen4_render_state_cleanup(ScrnInfoPtr pScrn)
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drm_intel_bo_unreference(render_state->wm_kernel_bo[i]);
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render_state->wm_kernel_bo[i] = NULL;
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}
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drm_intel_bo_unreference(render_state->sip_kernel_bo);
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render_state->sip_kernel_bo = NULL;
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}
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unsigned int
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