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Fix clock range for single-channel LVDS.

This commit is contained in:
Eric Anholt 2006-11-10 14:40:40 -08:00
parent dd1dcfab0a
commit d51555fba4
1 changed files with 4 additions and 1 deletions
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5
src/i830_display.c
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@ -189,7 +189,10 @@ i830FindBestPLL(ScrnInfoPtr pScrn, int pipe, int target, int refclk,
min_p1 = 1;
max_p1 = 8;
if (i830PipeHasType (pScrn, pipe, I830_OUTPUT_LVDS)) {
if (target < 200000) /* XXX: Is this the right cutoff? */
/* The single-channel range is 25-112Mhz, and dual-channel
* is 80-224Mhz. Prefer single channel as much as possible.
*/
if (target < 112000)
p2 = 14;
else
p2 = 7;