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xf86-video-intel
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Add DCC register dumping.

This commit is contained in:
Eric Anholt 2009-03-13 13:37:35 -07:00
parent a57814cc13
commit e0aba04da0
2 changed files with 29 additions and 0 deletions
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1
src/i810_reg.h
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@ -114,6 +114,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BITBLT_STATUS 0x01
#define CHDECMISC 0x10111
#define DCC 0x10200
#define C0DRB0 0x10200
#define C0DRB1 0x10202
#define C0DRB2 0x10204

28
src/i830_debug.c
View File

@ -53,6 +53,33 @@ DEBUGSTRING(i830_16bit_func)
return XNFprintf("0x%04x", (uint16_t)val);
}
DEBUGSTRING(i830_debug_dcc)
{
char *addressing = NULL;
if (!IS_MOBILE(pI830))
return NULL;
if (IS_I965G(pI830)) {
if (val & (1 << 1))
addressing = "dual channel interleaved";
else
addressing = "single or dual channel asymmetric";
} else {
switch (val & 3) {
case 0: addressing = "single channel"; break;
case 1: addressing = "dual channel asymmetric"; break;
case 2: addressing = "dual channel interleaved"; break;
case 3: addressing = "unknown channel layout"; break;
}
}
return XNFprintf("%s, XOR randomization: %sabled, XOR bit: %d",
addressing,
(val & (1 << 10)) ? "dis" : "en",
(val & (1 << 9)) ? 17 : 11);
}
DEBUGSTRING(i830_debug_chdecmisc)
{
char *enhmodesel = NULL;
@ -559,6 +586,7 @@ static struct i830SnapshotRec {
char *(*debug_output)(I830Ptr pI830, int reg, uint32_t val);
uint32_t val;
} i830_snapshot[] = {
DEFINEREG2(DCC, i830_debug_dcc),
DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
DEFINEREG_16BIT(C0DRB0),
DEFINEREG_16BIT(C0DRB1),