Commit Graph

1521 Commits

Author SHA1 Message Date
Jesse Barnes 53e3693ef1 Disable FBC by default on 965GM
Several people have reported that they see frequent FBC related display
corruption on 965GM, so disable it for now.  Users wanting to enable it can use
the driver option "Framebuffercompression" to override the default.
2007-11-14 16:24:56 -08:00
Jesse Barnes b2726899bc Add more FBC regs
Needed for the new debug code
2007-11-14 15:49:41 -08:00
Jesse Barnes b7bc694c6b Fix kernel get_brightness function
We need to look at "actual_brightness" rather than "brightness".  The former
contains the brightness value the kernel driver has actually set, while the
latter is merely what the user requested.
2007-11-14 15:46:57 -08:00
Jesse Barnes 9ee96ed02a Correct FBC debug message
To be consistent, it should say 'plane' rather than 'pipe'.
2007-11-14 15:44:56 -08:00
Jesse Barnes 675b9471d8 Add FBC registers to register dump output
Just for completeness.
2007-11-14 15:17:05 -08:00
Jesse Barnes a2a0821e74 Don't stop ring before restoring hw state
Some of the hw state restoration callbacks may want to use the ring for various
things like stopping video playback, so leave the ring enabled until we get
back from RestoreHWState.  Also rename the functions so that their purpose is
clearer and remove a couple of redundant lines.
2007-11-14 11:30:20 -08:00
Zhenyu Wang ad3bc0158d Don't enable fbc with XAA or tiling is off.
This slightly reworks my last fbc patch. We don't
support tiled front buffer with XAA now, so also
disable fbc on it. If tiled alloc failed, disable
fbc too.
2007-11-14 22:53:25 +08:00
Keith Packard 26194e19e1 Review PLL spreadsheet and update register ranges.
The PLL spreadsheet makes the precise register ranges allowed for each mode
quite clear, and shows a few inaccuracies in the b-spec. In particular, the
N register value may range from 1 to 6 instead of 3 to 8. This should close
the gap we've seen in the reachable frequencies.
2007-11-13 22:28:22 -08:00
Zhenyu Wang 581509321e Remove one redundant line. 2007-11-14 22:17:21 +08:00
Zhenyu Wang 8cea3c8cfa Don't setup fb compression if fb is not tiling 2007-11-14 22:17:21 +08:00
Jesse Barnes 539b669d6e Remove harmless error message
This really isn't an error in general.  If vblank pipe setup really fails for
some reason, it'll be obvious enough when the user tries to use vblank events
for something.

Patch from Hong Liu.
2007-11-13 17:59:54 -08:00
Jesse Barnes 43fbc54778 Improve backlight control
This commit fixes backlight support for several platforms.

Except on recent machines supporting the IGD OpRegion specification,
backlight control is rather platform specific.  In some cases, we can
program the native backlight control regsiters directly without any
trouble.  On others, we need to use the legacy backlight control
register.  On still others, we need a combination of the two.  And on
some platforms, none of the above will work, so we go through the
kernel backlight interface, which provides a platform specific driver
for backlight control.
2007-11-12 12:23:41 -08:00
Jesse Barnes 10988c5e6e Fix typo in PLL enable check
Check against DPLL_A instead of DPLL_B before writing PIPEACONF.

Thanks to Colin Guthrie for his sharp eyes.
2007-11-12 09:19:22 -08:00
Jesse Barnes ab2055ebb2 Add 'ret' variable to i830_allocator_init
Needed in the XF86DRI_MM case.
2007-11-09 13:55:46 -08:00
Jesse Barnes 24280edbdf Fixup warnings
Remove unused 'ret' variable, move pI830 under #ifdef XF86DRI_MM in
i830_allocate_memory.
2007-11-09 13:53:58 -08:00
Jesse Barnes 4fe507957b Remove unused 'palette_enable' variable 2007-11-09 13:51:11 -08:00
Jesse Barnes 62404a9c9c Update man page to reflect EXA by default 2007-11-09 07:55:53 -08:00
Jesse Barnes 177924e879 Bump driver version to 2.1.99 in preparation for 2.2 release 2007-11-08 18:16:48 -08:00
Jesse Barnes cb4e5796f0 Default to EXA
If EXA is compiled into the driver, default to using it for acceleration.
Hopefully we can remove XAA entirely one day.
2007-11-08 18:13:47 -08:00
Jesse Barnes 43a59ab26b Clear current video crtc on DPMS off
When calling the video DPMS off function, make sure we zero out the current
crtc so that it will be properly re-set up next time video is turned on.

Fix from Peter Clifton with changes by Keith Packard.
2007-11-08 16:52:41 -08:00
Jesse Barnes e784e152a8 Fix overlay destination clamping
The overlay width & height scaling clamp check was reversed.  Fix that and
update the comment.
2007-11-08 16:37:53 -08:00
Jesse Barnes b8770f7107 Setup 3D state at EnterVT time
In the absence of full suspend/resume support in the kernel, we have to
save/restore state in Enter/LeaveVT.  For 8xx chips, 3D state may be lost
during suspend/resume, so re-emit the basic setup at EnterVT time.

Patch from Peter Clifton.
2007-11-08 16:19:24 -08:00
Eric Anholt 5f92b4c2db Bug #12059: Add ch7019 to the list of supported devices for ch7017.
While I'm here, fix the chip description to be LVDS instead of TMDS in i2c
device.
2007-11-08 13:33:40 -08:00
Jesse Barnes eecd3ccede Check DPLL status before writing PIPEnCONF regs
If the DPLL isn't enabled or is in VGA mode, writing the PIPEnCONF registers
may cause a hang or crash.  So ensure the DPLL is in the proper state before
writing them.

Another excellent fix from Peter Clifton.
2007-11-08 09:31:08 -08:00
Jesse Barnes b434c1a437 Framebuffer compression fix: front buffer may not be at fence 0
Fix a long standing bug in the framebuffer compression code (thanks to
Pierre Willenbrock!) that prevented FBC from working correctly if the front
buffer was anywhere but fence register 0.
2007-11-01 12:06:07 -07:00
Zhenyu Wang 50d3693a68 Fix allocation reset for really not free BO allocator 2007-11-01 22:22:27 +08:00
Alan Coopersmith ecd995d533 Fix builds without DRI 2007-10-30 18:20:49 -07:00
Alan Coopersmith 7c88b58a93 Clear compiler error: "void functions cannot return values" 2007-10-30 18:20:15 -07:00
Thomas Hellstrom d2c78f82c2 Adapt to DRM Lockfree and setStatus changes. 2007-10-24 20:56:50 +02:00
Eric Anholt 78aaec0ffc Fix typo in my hand-application of rglowery's patch. 2007-10-24 11:50:54 -07:00
Rob 021265fbec Fix a crash in TV mode handling by initializing the prev field of modes. 2007-10-24 11:06:53 -07:00
Jesse Barnes 87345e820d intel_reg_dumper - dump VGA AR registers too
Add a VGA AR dumping function so we can debug text mode problems too.
2007-10-22 14:22:37 -07:00
Eric Anholt 78e251db67 In the clock graph, draw the VCO as erasures in the lines representing clocks.
This shows one of the reasons for the gaps: with the other settings, the VCO
is too low inside the gap.  However, it also points out another issue: we
aren't using the high end of the VCO range due to some other limits being hit.
2007-10-19 15:04:10 -07:00
Eric Anholt 9f9b888525 Warn in the log if we choose a PLL clock that's way out of line. 2007-10-18 11:29:24 -07:00
Eric Anholt 1f8bf11039 Add some nickle scripts for looking at PLL issues.
While here, move similar nickle scripts under src/scripts/
2007-10-18 11:29:24 -07:00
Eric Anholt 79636b8c77 Bump pciaccess version requirement for new API usage. 2007-10-17 17:10:46 -07:00
Dave Airlie c824c45e72 intel: make block handler hook happen no matter what video is in use
This shouldn't make a difference now, but for upcoming EXA/batch changes it
will be more useful
2007-10-17 16:35:29 +10:00
Rob aa88d23e61 AOpen 965GM mini pc has no LVDS 2007-10-17 09:19:19 +08:00
Kyle McMartin 38900f55e2 toshiba satellite u300 has no tv out 2007-10-16 16:38:28 -04:00
Michel Dänzer 74ac5de14e Adapt to libdrm buffer object API changes. 2007-10-16 15:08:26 +02:00
Eric Anholt d66e924680 In update_front_offset(), set pScrn->fbOffset even at EnterVT during init.
Failure to do so led to the memset() at EnterVT being done to an invalid
offset.
2007-10-15 11:31:51 -07:00
Jesse Barnes c94cdfd6dd Fix palette save/restore
When restoring the palette, we weren't checking to make sure the
associated pipe was enabled before writing the registers.  In some
configurations, this led to a driver crash.  Add new routines to handle
palette save/restore and verify that the pipes are on before we touch
the registers (could easily be changed to enable/disable the pipes
around the save/restore as well).
2007-10-13 15:57:45 -07:00
Eric Anholt e04333a635 Fix failure in tiling setup on non-power-of-two allocations on pre-965. 2007-10-12 16:14:52 -07:00
Eric Anholt a1612b7728 Use mprotect on unbound AGP memory to attempt to catch use while unbound.
This doesn't help with the most common use-while-unbound cases, which are
from the hardware side.
2007-10-12 16:14:50 -07:00
Eric Anholt 3af442ba52 Don't double-free the memory manager allocation. 2007-10-11 12:17:15 -07:00
Eric Anholt 6c485ff5bd Update memory manager sizing for the current set of LIFETIME_FIXED bufffers. 2007-10-11 12:17:15 -07:00
Eric Anholt d47cf14877 Move tiling fence register setup to bind time instead of allocate time.
This allows us to allocate tiled buffers in buffer objects.  In the process
I removed the fence division that we had for tiled buffers on pre-965.  If we
resurrect that code, it should probably be managed by just dividing all the
objects in roughly half and fencing those halves (to reduce the alignment
requirement), instead of using giant fences until we run out of space and then
trying to deal with scarce space on the last (or not) buffer.  Halving
our tiled objects would use 6/8 of our fence registers on that hardware.
2007-10-11 12:17:15 -07:00
Eric Anholt a6dc81a086 Allow front/back/depth to move over the lifetime of the server. 2007-10-11 12:17:15 -07:00
Eric Anholt 132dce7565 Delay SAREA and mapping setup until EnterVT when using the memory manager.
Otherwise, we would use uninitialized offsets in the early setup.
2007-10-11 12:17:14 -07:00
Eric Anholt 4ca3550fb7 Rework DRI buffer mappings and sarea setup to allow for moving buffers.
While this has been a desired feature for some time, to allow for reallocation
of the front buffer, it was made more necessary by the desire to avoid
requiring a NO_MOVE buffer type in TTM because buffer objects may not be left
pinned over VT switch.  This is a step towards making those buffers
movable and resizable.
2007-10-11 12:17:14 -07:00