Don't setup one-time mc context everytime, as the content is always
unchanged. And several structs got packed layout inside to ease static
state initialization.
When page flipping is enabled, we need to make sure any changes to the front
buffer are reflected in the back buffer(s) or corruption might occur at page
flip time. So make the damage handler work on 965 by adding appropriate tiling
flags and pitch adjustments.
The DRM supports disabling of vblank interrupts when not in use, but in order
to function properly it must also be aware of mode setting, which will reset
the frame counter to 0. Add code to call into the DRM before and after mode
setting, so that it can account for any lost vblank events.
HDMI, despite claiming to have pixel multiply support, actually doesn't
want it, at least in the way that SDVO did. Disable it.
Also disable the NULL_PACKETS_DURING_VSYNC bit. Despite the docs telling us
to set it, the output doesn't like it when you do that, and the BIOS doesn't
set it.
Also add a posting read to SDVOx setting. Without it, half the X starts
wouldn't get anything on the screen. (interestingly, it was every other
startup, not just a chance).
Besides not being #ifdef __linux__ed as requested, some linux kernels break
in exciting new ways when you try to mprotect from PROT_NONE back to
PROT_READ|PROT_WRITE. Yes, there are bugs in the code we're calling in a
bug-exploiting bug workaround.
If you want this workaround for the original bug exposed when moving to
libpciaccess, it's already in libpciaccess.
From the spec, only 965GM and IGD_GM have 128 FIFO entries.
With DSPARB change introduced by commit bd137a, I've got PIPE B
underrun when dual-headed on G35 platform.
It turns out 855 has a different DSPARB layout than 915+. And 945+ have more
FIFO entries, so we have to allocate things differently. So on 855 split the
FIFO evenly again between A & B planes, and do the same on 945, where we have a
larger FIFO. Fixes an issue reported by Daniel Stone with the previous default
value.
Add some debug code to catch FIFO underruns, which are normally bugs (unless
they occur during mode setting) and remove any plane C FIFO allocations, since
we don't use that plane at all. We may eventually need to be a little smarter
about this on platforms that use plane C for the popup.