Now, DDC modes always end up being preferred to custom modelines, even if
smaller. This should probably be fixed by inserting custom modelines into
the probed mode list if they're valid according to the probed parameters of the
monitor.
Too much code is lifted from static functions in xf86Mode.c, and those should be
made unstatic if possible. Using xf86ValidateModes is also rather hacky, and
I want to break the function down, but this is a first step.
This is the first stage of getting runtime monitor attachment. The old i830
GTF code is returned to use to provide suitable modelines for xf86ValidateModes
in the LVDS case, even though the LVDS doesn't care about the modeline and just
always programs its fixed values.
I had interpreted the docs as saying that the multiplier setting would further
divide the clock and stuff dummy bytes in. Instead, we have to set the DPLL at
the higher clock rate, and the pixel multiplier just controls the stuffing of
dummy bytes. Also, we have to set the multiplier both in the graphics chip and
on the SDVO device on the other side.
This method is slower (~5ms), but works on older chipsets. Also, load-based
detection is disabled, as it can be fooled by other outputs on the pipe being
active, such as LVDS.
New i915 drm ioctl (in version 1.5) allows the X server to select
which pipe drives vblank interrupts. Use this to drive from the 'preferred'
pipe. Yes, per-window vblanks would be nice in a shared fb environment.
Maybe someday.
Add lots of register debugging to track delta from BIOS settings.
Fix various mode settings to mirror BIOS sDVO values.
Disable analog/lvds output on pipe with sDVO.
Borrow Dave Airlie's I830xf86ValidateDDCModes code.
Fix various sDVO I2C messages to mirror Dave's code.
Also, pend bound computations to register writes to allow
updates to individual values that are 'out of spec' so
the client can update multiple values.
(cherry picked from 190f9ad060 commit)
Also, pend bound computations to register writes to allow
updates to individual values that are 'out of spec' so
the client can update multiple values.
control bus will reset from DDC mode to internal-registers mode after every
Stop afer a Start on the DDC bus. The xf86 DDC code causes multiple Start/Stops
in one probe. So, we create a wrapper bus that does the control bus switch at
every Start. It's not working yet on my hardware, but I'm pretty sure this is
the right way to go.
we have to set the sdvo register a lot earlier in order for them to sync
properly otherwise my monitor doesn't sync unfortunately, also
disable the sdvo while tweaking the PLLs.
This also comments out a setting that seems to break my system here for
Eric to look at later.
This destroys the i2c device properly if the device isn't detected,
and allows sDVO to work on GM chipsets, and doesn't initialise
the i2c bus twice for sDVO.
Eric Anholt
Keith Packard
Keith Packard
Lukáš Hejtmanek
Dave Airlie
Matthieu Herrb
Alan Hourihane
Ian Romanick