f71b9358b4
Cleanup tiling and FBC driver output.
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Remove an extra "FBC enabled" message from i830_memory.c (only report errors
if they occur), and don't print the "forcing FBC on" message if tiling was
already enabled, as it's redundant and confusing.
2007-08-10 15:53:04 -04:00
e6746d0f28
Enable tiling by default on 965.
2007-08-10 15:48:15 -04:00
e0fcf645a2
Tiling fixes for 965
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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
2007-08-10 15:43:06 -04:00
7b143e5c83
i965: increase composite vertex buffer size and alignment to be safe
2007-08-09 12:14:44 +10:00
14691b24da
i965: fix memcpy of the sf_kernel when a mask is needed
2007-08-09 09:41:32 +10:00
5e18c6af90
Allow 965 composite acceleration to A8 destinations.
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Note that this is a slowdown in text rendering due to the high overhead of our
compositing setup, but appears to be correct according to rendercheck.
2007-08-08 11:14:29 -07:00
b0ec670cdb
Bug #11593 : Remove dead struct vch_bdb_20 which was angering the sun compiler.
2007-08-08 11:03:51 -07:00
92af2f4bbc
Merge branch 'origin'
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Conflicts:
src/i830_exa.c
2007-08-07 15:18:17 -07:00
da82a47a55
Fix EXA rendering with tiled front buffer on pre-965.
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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
2007-08-07 15:13:10 -07:00
e0be352f50
Fixup pitch in Prepare* functions, since actual hooks may
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be called many times for the same pixmap, and we don't want
to keep dividing the pitch by 4.
2007-08-07 12:42:42 -07:00
7431abee5f
Define INTEL_VERSION_MAJOR/MINOR/PATCH using PACKAGE_VERSION_*
2007-08-07 09:13:00 +02:00
9e1914270a
Remove 4k offset checks from Copy & Solid hooks.
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Reading the docs too literally can cause you to hide bugs with false fixes...
2007-08-06 17:55:00 -07:00
3510d5728f
Fix accumulated whitespace nits in i830_exa.c
2007-08-06 16:44:39 -07:00
5ff05dffe2
More tiled rendering fixes: - check for tiling, not just offset in PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
2007-08-06 16:04:12 -07:00
ba90d94432
Add the file mode for bios_dumper output so it doesn't have 000 permissions.
2007-08-06 14:34:58 -07:00
322a163cfb
Quirk away the nonexistent TV connector on the Panasonic CF-Y4.
2007-08-06 14:34:57 -07:00
ffbab2ee5d
Limit Solid & Copy offsets to 4k when rendering to tiled targets
2007-08-03 21:27:52 -07:00
019dbfda29
Merge branch 'master' of ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
2007-08-03 20:45:14 -07:00
3d3c0e8c55
Tiled rendering & fbc fixes:
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
2007-08-03 20:40:45 -07:00
0da4f2b0cd
Legacy backlight changes:
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
2007-07-31 16:22:36 -07:00
15f71edba3
Update Lenovo TV quirk info
2007-07-28 17:43:29 +08:00
f403a50afb
Add another Lenovo TV output quirk
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From issue report http://lists.freedesktop.org/archives/xorg/2007-July/026644.html
2007-07-27 09:24:24 +08:00
34c82ad7ce
Add quirk support
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This one trys to use a flag for possible quirks. It adds a quirk
for my Lenovo T61 TV output, and ports some origin LVDS quirks to it.
2007-07-27 09:14:13 +08:00
0fd3ba0518
Fix typo in intel.man
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Reported by A. Costa" <agcosta@gis.net> in
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=432061
2007-07-25 20:11:32 +02:00
45962eed51
Fix a typo in i915 render
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Fence setting is in mapstate actually. This fixes rotation in
tiled fb case, thanks Keith to report this.
2007-07-23 09:50:17 +08:00
b1af2c0e01
Fix device id info for 945GME, 965GME
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which do have new host bridge ids
2007-07-20 15:18:48 +08:00
c7920a0e81
strip out remainder of drmmm code in driver
2007-07-19 15:09:54 +10:00
37652b6888
intel: oops I commited pixman local workaround - undo it
2007-07-17 14:03:21 +10:00
e40f6a4923
intel: actually 2.3.1 should be good enough
2007-07-17 09:20:07 +10:00
1e169be25b
intel: don't try and use TTM memory manager with old libdrm interface
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I probably need to release a libdrm with this interface in it now..
2007-07-17 09:17:31 +10:00
ff2be3995d
Remove hard-coded CRT blanking frobbing for load detection.
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CRT blanking needn't be adjusted to perform load detection on 9xx chips, and
the 8xx load detection path now adjusts blanking just during load detection.
Adjusting the blanking interval turned out to cause many monitors to fail to
sync.
2007-07-13 13:39:36 -07:00
00f4587025
Ensure pipe/output active before doing load detection.
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If the pipe or output have been set to DPMSOff, then load detection will not
work correctly. Also, share the load detection configuration code between
crt and tv outputs.
2007-07-13 13:39:36 -07:00
6f18300aed
Eliminate bogus (and harmful) blanking adjustment for load detect.
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Instead of always adding blanking to mode lines, use the FORCE_BORDER option
on i9xx hardware where it works, and dynamically add a bit of border if
necessary on i8xx hardware to make load detection work. This may cause
flashing when a usable crtc is not otherwise idle when load detection is
requested.
2007-07-13 13:39:36 -07:00
04130ac6b7
Fix i915 rendering for tiled buffer
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Make it to check fence register for dest buffer.
2007-07-11 11:42:56 +08:00
88f8b688e2
Fix some physical address handling for >4GB addresses.
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The upper bits would have been inappropriately dropped on G33-class hardware,
and on G965-class hardware in a 32-bit environment. The only use of physical
addresses on these should be for FBC, though, and FBC requires addresses
below 4GB. This is unresolved.
2007-07-09 13:01:12 -07:00
bf831117b4
FBC fixes:
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- allow FBC and Tiling to be forced off if configured to do so
- only touch FBC registers if pI830->fb_compression is true
2007-07-07 10:15:32 -07:00
b426866fe1
Fix manpage to reflect default behavior.
2007-07-06 20:48:40 -07:00
377c58373d
Fix naming of FBC plane enable bits (mistakenly called them pipes earlier).
2007-07-06 20:39:19 -07:00
9c0388dc8d
Update man page with current behavior.
2007-07-06 20:38:41 -07:00
cecbc71fdc
Fix debug output in fbc enable/disable routines. Add logic to make sure fbc
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isn't enabled twice on two different pipes.
2007-07-06 16:36:34 -07:00
4359df9419
Fix tiling and fb compression defaults for 965 (not yet fully supported).
2007-07-06 16:17:45 -07:00
ca593a5219
FBC and tiling changes
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- change framebuffer option name to "FramebufferCompression"
- add new "Tiling" option (controls all tiling, not just front buffer)
- add debug message to fb compression enable/disable routines
- update man page with new options
2007-07-06 16:10:52 -07:00
8798ef1132
Merge branch 'master' into fbc
2007-07-05 12:21:31 -07:00
8919b22921
Re-add tiling kludge, but only for 965.
2007-07-05 12:21:06 -07:00
407b124af8
Remove tiling kludge. May need more fixes for 965.
2007-07-05 11:31:34 -07:00
7a87b9d2a2
Revert discard alpha change, requires other fixes to work.
2007-07-05 11:23:06 -07:00
fecf964534
FBC fixes:
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- properly check several FBC enablement constraints
- don't use alpha discard if FBC is in use
2007-07-05 10:59:23 -07:00
60ee7b6a91
Fixup line length buffer padding, add kludge for front buffer tile
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pitch.
2007-07-03 14:20:34 -07:00
3c552af65d
Update documentation and bump driver version to 2.1.0.
2007-07-02 18:33:47 -07:00
f02036aedc
Framebuffer compression changes:
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- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
2007-07-02 15:42:02 -07:00
Jesse Barnes
Dave Airlie
Dave Airlie
Carl Worth
Eric Anholt
Brice Goglin
Zhenyu Wang
Brice Goglin
Keith Packard
Jesse Barnes
Jesse Barnes