Commit Graph

15 Commits

Author SHA1 Message Date
Eric Anholt 79e59fb2a0 Add support for Ivybridge chipset.
This gets display and 2D blit acceleration up and running.  No Render
acceleration is provided yet.
2011-05-09 22:56:42 -07:00
Chris Wilson 3145530fee Ensure that the partial batch is flushed upon the blockhandler
Currently, we require that a batch containing a dirty bo be submitted
before we mark the device as requiring a flush. So if we never submit a
batch between block handlers, we can end up sleeping without ever
flushing either the partial batch or the rendering to the scanout.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36776
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-07 20:04:18 +01:00
Chris Wilson 97e9557619 intel: Restore manual flush for old kernels
Daniel Vetter pointed out that the automagic flush by the kernel for the
busy-ioctl was only introduced upstream in 2.6.37. So we still need to
manually emit a flush on old kernels.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-08 13:38:48 +01:00
Daniel Vetter fb40bf2b33 Tell users to grab i915_error_state on gpu hangs
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-04-08 12:37:35 +02:00
Chris Wilson 25521900df gen6: Invalidate texture cache
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-07 15:09:30 +01:00
Chris Wilson 6f104189bb Take advantage of the kernel flush for dirty bo in the busy ioctl
Rather than just creating and submitting a batch that simply contains a
flush in order to periodically ensure that rendering reaches the
scanout, we can simply ask the kernel whether the scanout is busy. The
kernel will then submit a flush on our behalf if it is dirty, which
takes advantage of the kernel's dirty state tracking.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 19:24:30 +01:00
Chris Wilson 79444291a3 i965: segregate each vertex element into its own buffer
Reduce the number of relocations emitted by only emitting one relocation
per vertex element per vertex buffer.

References: https://bugs.freedesktop.org/show_bug.cgi?id=35733
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 16:42:57 +01:00
Chris Wilson 55c5f1876e Wait on the current buffer to complete when running synchronously.
And remove the vestigal wait upon changing crtc as this is more properly
done in the kernel.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson 3cc74044ce i965: Amalgamate surface binding tables
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson a1fa0dbfda i965: Upload an entire vbo in a single pwrite, rather than per-rectangle
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson a44a63d2ff Wait for any pending rendering before switching modes.
A perennial problem we have is the accursed WAIT_FOR_EVENT hangs, which
occur when we switch the framebuffer before the WAIT_FOR_EVENT completes
and upsets the GPU.

We have tried more subtle approaches to detected these and fix them up in
the kernel, to no avail. What we need to do is to delay the framebuffer
flip until the WAIT completes, which is quite tricky in the kernel
without new ioctls and round-trips. Instead, apply the big hammer from
userspace and synchronise all rendering before changing the framebuffer.
I expect this not to cause noticeable latency on switching modes (far
less than the actual modeswitch) and should stop these hangs once and
for all.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31401 (...)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-05 10:07:46 +00:00
Zou Nan hai 5bed685f76 add BLT ring support
gen6+ platform has a BLT engine with seperate
command streamer to support BLT commands.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[ickle: merge trivial conflict]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01 10:37:51 +00:00
Xiang, Haihao 3213849907 Xv: setup pipeline for Xv on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:51:13 +08:00
Chris Wilson 4083197a44 Include a chipset generation number to clarify device specific paths.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-07 13:26:07 +01:00
Chris Wilson 5c663ce844 Rename common infrastructure to the intel namespace.
After splitting out the i810 driver into its own legacy directory, we
can identify the common routines not as i830 but as intel. This
clarifies the code which *is* i830 specific.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-25 13:18:01 +01:00