Mixing I915_TILING_Y and the blitter is painfully slow, so we need to
take use of I915_TILING_Y into more prominent consideration and even
force a ring switch in case it is being used.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when
the running with > 8bpc.
v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc
v3: Fix the vg "bluered" typo (Mario)
This time I even build tested with vg support
Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Generalize the code that parses the plane properties to be useable
for crtc (or any kms object) properties as well.
v2: plane 'type' prop is enum not range!
Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Once we've switched to using the swcursor (possibly
due to the cursor ioctl failing) we currently keep
using the swcursor until the modeset.
That's not particularly great as the swcursor has several
issues. Apart from the (presumably expected) flicker,
the cursor also tends to leave horrible trails behind
around dri2/3 windows (happens with tearfree at least).
To avoid some of that let's try to switch back to the hwcursor
a bit sooner. We can do that neatly via the convenient swcursor
block handler.
v2 [ickle]: Apply the restoration after the screen update is complete.
v3 [vsyrjala]: Push it back to restore_swcursor and remove the
fullscreen redraw -- prevents terrible flickering in v2!
References: https://bugs.freedesktop.org/show_bug.cgi?id=106935
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Apparently we never take this path or else it would have failed before
(we don't take it as we prefer render for these chipsets).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Presumably this only matters for i686 because amd64 implies sse2, but:
BUILDSTDERR: In file included from gen4_vertex.c:34:
BUILDSTDERR: gen4_vertex.c: In function 'emit_vertex':
BUILDSTDERR: sna_render_inline.h:40:26: error: inlining failed in call to always_inline 'vertex_emit_2s': target specific option mismatch
BUILDSTDERR: static force_inline void vertex_emit_2s(struct sna *sna, int16_t x, int16_t y)
BUILDSTDERR: ^~~~~~~~~~~~~~
BUILDSTDERR: gen4_vertex.c:308:25: note: called from here
BUILDSTDERR: #define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y) /* XXX assert(!too_large(x, y)); */
BUILDSTDERR: ^~~~~~~~~~~~~~~~~~~~~~~~
BUILDSTDERR: gen4_vertex.c:360:2: note: in expansion of macro 'OUT_VERTEX'
BUILDSTDERR: OUT_VERTEX(dstX, dstY);
BUILDSTDERR: ^~~~~~~~~~
The bug here appears to be that emit_vertex() is declared 'sse2' but
vertex_emit_2s is merely always_inline. gcc8 decides that since you said
always_inline you need to have explicitly cloned it for every
permutation of targets. Merely saying inline seems to do the job of
cloning vertex_emit_2s as much as necessary.
So to reiterate: if you say always-inline, it won't, but if you just say
maybe inline, it will. Thanks gcc, that's helpful.
In case udev_monitor_get_device() itself does not handle being
interrupted, go around the loop again. Daniel Vetter discovered this
interesting quirk during igt testing of kms_leases.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
The various clut handling functions like a setup
consistent with the x-screen color depth. Otherwise
we observe improper sampling in the gamma tables
at depth 30.
Therefore replace hard-coded bitsPerRGB = 8 by actual
bits per channel scrn->rgbBits. Also use this for call
to xf86HandleColormaps().
Tested for uxa and sna at depths 8, 16, 24 and 30 on
IvyBridge, and tested at depth 24 and 30 that xgamma
and gamma table animations work, and with measurement
equipment to make sure identity gamma ramps actually
are identity mappings at the output.
v2: Also deal with X-Server 1.19 and earlier, which as of
v1.19.6 lack a fix to color palette handling and can
not deal with depths/bpc > 24/8 bpc. On < 1.20 we skip
xf86HandleColormaps() setup at > 8 bpc. This disables
color palette handling on such servers at > 8 bpc, but
still keeps RandR gamma table handling intact.
Tested on 1.19.6 and 1.20.0 to do the right thing.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
The kernel may keep the old connector id around so that userspace can
gracefully switch it off, which means that on detecting a topology
change (a new id for an old connector path), we must do a SetCRTC to
release the old resources.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106250
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
OpenBSD, FreeBSD and NetBSD don't contains file byteswap.h.
Used specifics of them.
Fixes: 746ab3bb13 (sna: Added AYUV format support for textured and sprite video adapters.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109268
CC: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
If we do not have a mode (and bo) enabled on the crtc, then trying to
restore that bo ends up in a NULL pointer dereference.
Reported-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
v2: Renamed DRM_FORMAT_XYUV to DRM_FORMAT_XYUV8888.
Added comment about AYUV byte ordering in Gstreamer.
v3: Removed sna_composite_op flags related change to the separate patch.
v4: Fixed review comments, done code refactoring
v5: Fixed following review comments:
- Fixed comment in shader code for ayuv kernel.
- Fixed naming to VIDEO_AYUV_BT601/BT709 for ayuv kernels.
- Removed duplicate gen9_kernel parameter, left from previous patches
- Added colorspace handling for new AYUV kernel
- Fixed naming of sna_copy_packed_data_ayuv to sna_copy_ayuv_data
- Started using standard bswap_32 function for byte swapping in sna_copy_ayuv_data
- Removed redundant code in sna_copy_ayuv_data so that it looks more neat
- Fixed XVIMAGE_AYUV structure initialization to contain proper byte sequence for GST
- Fixed bogus comment about subsampling for DRM_FORMAT_XYUV8888
- Fixed AYUV advertisement for all platforms
- Removed unnecessary RGB888 declaration.
v6:
- Fixed surface format not to use alpha as supposed
- Now doing byte swapping always during copy
- Changed hack, required for GST to work to be at one place
- Fixed invalid sampling values for XVIMAGE_AYUV
- Fixed sprite format checking order and images_ayuv definition.
v7:
- Removed reverse_bytes bool parameter, now swapping bytes
for XYUV unconditionally both for textured and sprite modes.
v8:
- Added gen9_images structure, in order to expose AYUV format to
proper platforms.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
With the extra video kernels we already ran out of bits in
the flags. To tackle that let's just split out the
wm_kernel to its own thing.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
We can't output color index formats with the render engine,
so let's disable the textured Xv adaptor for depth 8.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Texured Xv works just fine with depth 30. Allow it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
With the colorkey setup fixed the sprite Xv adaptor works just
fine with depth 30.
With depth 8 there is one remaining problem with the usage of
the LUT for gamma vs. C8, but that is purely a kernel issue.
Let's allow both depth 8 and depth 30 with the sprite Xv
adaptor.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Set up the colorkey correctly for depth != 24. For 8bpc we
need to replicate the same key value into each channel, for
depth 15/16 we need to mask off the unused low bits in each
channel, and for depth 30 we just use the 8 msbs of each channel
as the colorkey register can't hold the full 10 bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
'debug' is a reserved option name since meson 0.48. So we
must rename our own debug option to something else. Let's
go with 'internal-debug'.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
If Xinerama is enabled, RandR is disabled and calling into RR functions
merely explode, so don't.
Reported-by: Mariusz Białończyk <manio@skyboo.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108495
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Sometimes the write simply do not land until later, requiring us to be
very careful in how we perform domain tracking.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Import the kernel's i915_pciids.h, up to
commit d0e062ebb3a44b56a7e672da568334c76f763552
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Fri Aug 3 16:27:21 2018 -0700
drm/i915/cfl: Add a new CFL PCI ID.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Add more Coffeelake PCI IDs based on the following kernel patch:
commit c99d7832dcd7423ba352386107118b9bd8b83158
Author: Rodrigo Vivi <rodrigo.vivi@intel.com>
Date: Wed Dec 20 10:29:19 2017 -0800
drm/i915/cfl: Adding more Coffee Lake PCI IDs.
Signed-off-by: Liwei Song <liwei.song@windriver.com>
It's 32bpp, depth 24 (for x8r8g8b8 pixel format), not 32 for everything.
Just to be on the safe side, pick the more common x8r8g8b8 format.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Looks like we need a libdrm dep on intel_drv. Build fails for me on
Arch.
In file included from ../src/intel_device.c:51:
/usr/include/xf86drm.h:40:10: fatal error: drm.h: No such file or directory
#include <drm.h>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
On SKL+ the dst colorkey is enabled on the primary plane instead of the
sprite plane. That means the restriction of scaling vs. keying doesn't
actually apply here as we never scale the primary. So let's remove
the requirement of having XV_ALWAYS_ON_TOP enabled to get hw scaling.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
When we're trying to reinstate the colorkey we might fail on account of
the plane still being enable with a configuration that prevent the
use of colorkey. This happens easily with NV12 since the plane scaler
required by even unscaled NV12 is not compatible with colorkey.
To work around the problem let's try disabling the plane first, then
re-enable the colorkey, and finally we will try to re-enable the plane.
The plane re-enable may fail, in which case we'll head to the GPU
scaling fallback path. The cost is a flash of the colorkey when the
plane blink off and then back on.
Help me atomic ioctl, you're my only hope!
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Even unscaled NV12 needs the plane scaler on SKL+, so when
unscaled NV12 setplane fails we should still take the GPU
scaling fallback path.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Starting from ~KBL planes can do NV12. Let's make use that
capability in the sprite Xv adaptor.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Not all sprite planes support RGB565. Insrtead of hardcoding which
platforms have it let's ask the kernel instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
On SKL+ dst color keying only works between the first sprite and the
primary. We probably wante the first Xv port to be the first sprite
plane so that the user gets working colorkeying for the port that is
most likely to be used first. No way to get dst colorkeying with the
other ports :(
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Allow the client to select between BT.601 and BT.709 via the
XV_COLORSPACE port attribute with the textured Xv adaptor as well.
Since the BT.601 coefficients are currently hardcoded in the
yuv->rgb shader, let's just add a mostly duplicated shader with
hardcoded BT.709 coefficients instead. Not the most elegant solution
but avoids having to touch any state setup etc.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Our current yuv->rgb shaders follow the BT.601 conversion formula.
Rename the shader sources to indicate that fact.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
exa_wm_yuv_rgb.g5a is identical to exa_wm_yuv_rgb.g4a. Just use a
symlink intead of duplicating the whole file.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
We only need DRI1 to support UMS on i810, but modern Xservers don't
support DRI1 and the support infrastructure is no longer being shipped
on some distributions. Gracefully fail if we can't compile the DRI1
code blocks for i810.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Add the Coffeelake PCI IDs based on the following kernel patch:
commit d29fe702c9cb682df99146d24d06e5455f043101
Author: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Thu Jun 8 16:41:07 2017 -0700
drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.
Signed-off-by: Liwei Song <liwei.song@windriver.com>
Add the Coffeelake PCI IDs based on the following kernel patches:
commit ccfd13215fd25a0e8c28221f3acc0dcaec11cd15
Author: Anusha Srivatsa <anusha.srivatsa@intel.com>
Date: Thu Jun 8 16:41:06 2017 -0700
drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.
Signed-off-by: Liwei Song <liwei.song@windriver.com>
The kernel may reject the setplane due to eg. exceeding the max
downscaling limit of the hardware. In that case let's retry the
operation but let the GPU do the scaling for us.
Tested on my IVB, after hacking the kernel to reject setplane
which exceeds the max hw downscaling limit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
video->plane is never populated so nuke it. Its only user can be nuked
as well since all it's trying to do is turn off the plane (which fails
on account plane_id being zero). We don't need to disable the plane
immediately upon the setplane failure as the higher level code will
end up stopping the entire port on error, and thus the plane will get
disabled just fine.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
TimerSet scales linearly with the number of elements in the queue as it
performs an insertion sort, duplicating the sorting we also perform to
keep the per-crtc vblank queue in an orderly fashion. As we already
maintain the ordered timeline of vblanks, we can simply queue the next
when the current vblank completes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
If the device is already wedged (no GPU), jump straight to the swrast
path for performing the per-crtc transformations.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105420
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Having just chased a bug along this path, I found the following debug
helpful in a narrowing down why certain paths were chosen.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
We were telling the kernel the correct location for it to fill the
64b relocation, but we were writing the presumed offset into the wrong
pair of dwords in the batch ourselves. For the frequent case where we
used a new upload buffer, the kernel would perform the fixup and correct
our mistake, but if we happened to reuse a buffer then we told the gpu
to source the stipple from the wrong address.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105886
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
When we mix TearFree and per-crtc pixmaps (e.g. for RandR transformations),
we stash the old buffer on the CRTC for double buffering. However, this
buffer needs to be reallocated when we change output resolutions, as the
CRTC size may change.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
kgem_bo_map__(cpu|gtt) leaves the sync up to the caller, in particular
so that the obtaining the pointer and controlling the cache domains are
not conflated and can be separated. However, it does mean that the
caller can not assume that obtaining the pointer updates the cache
domains, as it does not. memcpy_copy_boxes fell into this trap.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
TearFree wants to grab the most recently used scanout for rendering the
next frame into. If the flip event was still pending, we would then
query the drm event buffer for any pending completions, but this would
proceed to execute all the other events before the flip events as well.
Since we they were out of sequence, we pushed them into a buffer to
execute afterwards, however we forgot the side effects of the flip
handlers, for example see commit af36a4ab78 ("sna: Defer submission
of the next shadow frame until halfway through") and that there may have
been events read from drm into a local buffer inside sna_mode_wakeup()
that haven't been processed yet.
Eliminate the need for calling sna_mode_wakeup() by ensuring that all
flip events have been completed first before handing the vblank
callbacks and potential drawing, ensuring the correct ordering.
References: https://bugs.freedesktop.org/show_bug.cgi?id=105720
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
We shouldn't even be attempting to redisplay if there are flips pending,
so exit early and expect to be called again after the pending flips
complete. Exiting early avoids having to call sna_mode_wakeup() in what
used to be a potentially recursive manner (see commit af36a4ab78
"sna: Defer submission of the next shadow frame until halfway through").
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Do not try and workaround the failure by forcing the wait-for-flip as we
may be inside a vblank handler already. Just report the move failed and
expect the caller to skip the draw, fairly standard practice for
allocation failure handling (stale output rather than crash).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Do not immediately post the next shadow flip on completion of the
current flips, but instead queue a timer for half way through the next
vblank so that try to we keep the additional input-output lag to less
than a frame.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Chris Wilson
Ville Syrjälä
Adam Jackson
Mario Kleiner
Sergii Romantsov
Stanislav Lisovskiy
Liwei Song