Commit Graph

5682 Commits

Author SHA1 Message Date
Chris Wilson 4bad76b451 sna/dri: Don't force ring selection if we have semaphores
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 14:32:04 +01:00
Chris Wilson fb7b584ec9 sna/dri: Correct ring selection for a busy bo
Confused the RENDER ring with the BLT, limiting swap performance.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 14:32:04 +01:00
Chris Wilson 20e58077fe sna/gen6: Reduce ring switching for overlapping copy boxes
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 11:21:10 +01:00
Chris Wilson 2345227663 sna/gen7: Use a temporary to avoid switching rings for overlapping copies
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 11:12:12 +01:00
Chris Wilson 61ec2999af sna/gen4: Restore w/a flush for video
One flush removal too many, keep those fingers crossed that the others
do not make an unwanted return.

Reported-by: Roman Jarosz <kedgedev@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53119
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 10:34:49 +01:00
Chris Wilson 5833ef173a 2.20.3 release
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 09:32:35 +01:00
Chris Wilson 036b90f099 sna/gen7: Correct number of texture coordinates used for video
Fixes regresion from

commit 33c028f8be
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Aug 1 01:17:50 2012 +0100

    sna/gen6+: Reduce floats-per-vertex for spans

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 21:42:28 +01:00
Chris Wilson 05dcc5f169 Pass the chipset info through driverPrivate rather than a global pointer
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 21:42:28 +01:00
Chris Wilson 2b3f4ca33a Unexport intel_chipsets
Only used by the core module code, so make it static.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 21:42:28 +01:00
Chris Wilson 5ff749727d sna/gen7: Add constant variations and hookup a basic GT descriptor for Haswell
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 12:26:12 +01:00
Chris Wilson cd028cad3d sna: Limit the batch size on all gen7 variants
Seems the limit on the surface state size is common across the family

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 12:21:46 +01:00
Gwenole Beauchesne 4cd9ec9d40 uxa: fix 3DSTATE_PS to fill in number of samples for Haswell
The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen6_upload_invariant_states().

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:29 +01:00
Gwenole Beauchesne 412668464c uxa: set "Shader Channel Select" fields in surface state for Haswell
For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:26 +01:00
Gwenole Beauchesne a47ba68996 uxa: fix max PS threads shift value for Haswell
The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:23 +01:00
Gwenole Beauchesne ce4421e175 uxa: use at least 64 URB entries for Haswell
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:18 +01:00
Gwenole Beauchesne 8c880aa34c uxa: add IS_HSW() macro to distinguish Haswell from Ivybridge
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-08-03 12:11:59 +01:00
Gwenole Beauchesne 0c0d1d956a Introduce a chipset identifier for Haswell (Ivybridge successor)
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-08-03 12:10:54 +01:00
Chris Wilson 146959dd5e sna: Drop the clear flag as we discard the GPU damage
Hopefully only to keep the sanity checks happy...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 23:44:05 +01:00
Chris Wilson 7404e3085b sna: Ensure we only mark a clear for a fill on the GPU bo
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 23:39:13 +01:00
Chris Wilson ca46d1c7a1 sna/gen7: Prefer the BLT for self-copies
Looking at the test results for a third time, gives the edge to the BLT
again.
2012-08-01 20:21:45 +01:00
Chris Wilson e4a3cd3d16 sna: Add validation of the clear flag to pixmap debugging
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 17:37:33 +01:00
Chris Wilson eaeda34bef sna: Fix computation of st values for SIMD8 dispatch
Fixes regression with enabling 8-pixels.

Reported-by: Mehran Kholdi <semekh.dev@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53044
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 16:23:05 +01:00
Chris Wilson 55231eca81 sna/gen6: Install a fallback 16-pixel shader
In case the DBG options leave no shader compiled, make sure we always
supply one.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 16:22:23 +01:00
Chris Wilson 4e79c1fef0 Revert "sna/gen7: Prefer the BLT for self-copies"
This reverts commit 89e75dbcb6.

Having removed the forced stall for a RENDER self-copy there is no
longer a need to encourage ring switching.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 16:00:05 +01:00
Chris Wilson 85cef78a40 sna/gen7: Simplify the force-stall detection
After reducing the number of conditions where we think we need to force
the stall on the results, we can then simplify the code to detect
that remaining case.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 13:40:42 +01:00
Chris Wilson 9391a2c71f sna/gen7: Only force a stall for a dirty target if also used as a blend source
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 12:50:32 +01:00
Chris Wilson 0a4bb8663b sna/gen4: Flush not required between fill vertices, only nomaskcomposite
A small breakthrough... Still need to flush the primitive between state
changes though.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 11:32:01 +01:00
Chris Wilson 33c028f8be sna/gen6+: Reduce floats-per-vertex for spans
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 11:01:38 +01:00
Chris Wilson 9b2873d3d9 sna/gen4+: Implement an opacity shader
Avoid the cumbersome lookup through the alpha gradient texture and
simply multiply the incoming opacity value. The next step will be to
reduce the number of floats required per vertex.

Now that we have removed the primary user of the alpha solid cache, it
may be time to retire that as well.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 10:32:37 +01:00
Chris Wilson fd3a123605 sna/gen6: Enable 8 pixel dispatch
This gives a small performance increase when operating with rectangles,
which is reasonably frequent.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-31 19:11:54 +01:00
Chris Wilson 8922b804bc sna/gen7: Enable 8 pixel dispatch
This gives a small performance increase when operating with rectangles,
which is reasonably frequent.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-31 19:11:54 +01:00
Chris Wilson 492093d04b sna: Generate shaders for SNB+ 8-pixel dispatch
Not ideal yet, sampling an alpha-only surface using SIMD8 only seems to
ever return 0...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-31 19:11:08 +01:00
Chris Wilson 6a5ed88f9f sna/gen4: Tidy debugging code
Cluster the ifdefs together in the initialisation code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-31 17:45:20 +01:00
Chris Wilson 46ec9b0ed5 sna: Update DPMS mode on CRTC after forcing the outputs on
If we forcibly update the outputs to be on, then the core will not issue
its on DPMS event and we miss out on updating the CRTC bookkeeping in
sna_crtc_dpms(). So we need to update the flag on the CRTC as we
manipulate the outputs during modesetting.

References: https://bugs.freedesktop.org/show_bug.cgi?id=52142
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-31 17:45:20 +01:00
Chris Wilson 8f166d26b8 sna: Be more careful with damage reduction during CompositeRectangles
We actually need to force DAMAGE_ALL in case we are promoting the GPU
pixmap.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-31 13:11:46 +01:00
Chris Wilson e6cb5d93ea sna: Avoid overlapping gpu/cpu damage with IGNORE_CPU
We cannot simply ignore the presence of CPU damage with IGNORE_CPU but
must remember to discard it.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 13:12:05 +01:00
Chris Wilson c9805ba987 sna: Export sna_drawable_use_bo() to select target for FillRectangles
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 13:12:05 +01:00
Chris Wilson 89e75dbcb6 sna/gen7: Prefer the BLT for self-copies
If we are copying to ourselves, we have to regularly flush the render
cache at which point the RENDER pipeline is slower than the BLT
pipeline.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 13:12:04 +01:00
Chris Wilson 33d6afda6c sna/gen7: Compile basic kernels at runtime 2012-07-30 13:12:04 +01:00
Chris Wilson eba8d3b3e1 sna/gen6: Compile basic kernels at runtime 2012-07-30 13:12:04 +01:00
Chris Wilson 8515ec9040 sna/gen5: Compile basic kernels at runtime 2012-07-30 13:12:04 +01:00
Chris Wilson 00c08b1842 sna/gen4: Compile basic kernels at runtime 2012-07-30 13:12:04 +01:00
Chris Wilson 7c9dbc980b sna: Assemble SF and WM kernels using brw
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 13:12:04 +01:00
Chris Wilson 8ebafa0493 sna: Add the brw assembler
In order to construct programs on the fly to cater for the combinatorial
number of possible shaders, we need an assembler, whilst also taking the
opportunity to remove some of the inefficiencies and mistakes from the
current shaders.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 12:57:13 +01:00
Chris Wilson ca9d9c02a2 sna: Prefer not to create a GPU bo without RENDER acceleration
Unless that bo happens to be used on a render chain to the scanout.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 11:02:36 +01:00
Chris Wilson eefbe5b603 sna: Debug option to test migration of inactive pixmaps
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-30 10:56:29 +01:00
Chris Wilson d3499cacb5 sna: Assert that we never attempt to submit a batch whilst wedged
We should be asserting at the point that we insert the invalid operation
into the batch, but asserting upon submitting the batch is a useful
failsafe.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-29 23:00:15 +01:00
Chris Wilson cb4d789f98 sna: Disable the warning for a hung GPU is we manually set wedged
Only warn about a hung GPU if we encounter an EIO during operation, but
don't warn if we set wedged during initialisation based on unsupported
hw or user request.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-29 22:55:44 +01:00
Chris Wilson 0fd680ff52 Don't disable acceleration on 830/845g by default
Run the risk of a GPU hang (it shouldn't endanger the entire machine
normally) and let the user elect to disable it through

  Option "NoAccel" "true"

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-29 22:51:26 +01:00
Chris Wilson 3d45f0affe sna: Honour the Option "DRI"
References: https://bugs.freedesktop.org/show_bug.cgi?id=52624
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-07-28 18:21:08 +01:00