- Use the existing single/dual-channel state when available, as changing it
doesn't appear to work out.
- Set the power state of the CLKB and B0-B3 pairs according to whether
choose to go dual-channel or not.
- Restore the LVDS register at the appropriate point (before DPLLs are
re-programmed.
This gets correct clocks detected on most harware. The SSC is always assumed
to be 66Mhz, which may not be true, but we'll fix that when we find example
hardware.
This includes not reporting some fields on hardware where those bits are
reserved, correcting one of the hardware error bit numbers, and reducing
the severity of the debugging output warnings.
Autodetect libdrm version, disable new memory manager on older libraries.
Move new M_T_ defines from i830.h to i830_xf86Crtc.h. Add many system
headers to define functions. Use i830PipeSetBase at end of mode setting
code to set DSP*BASE and flush changes. Don't duplicate PipeSetBase call
from screen init function. Make initial RandR configuration code usable on
older versions of extension so the server doesn't start in a panning mode.
Use xfree instead of free in i830_tv.c.
Add lots of register debugging to track delta from BIOS settings.
Fix various mode settings to mirror BIOS sDVO values.
Disable analog/lvds output on pipe with sDVO.
Borrow Dave Airlie's I830xf86ValidateDDCModes code.
Fix various sDVO I2C messages to mirror Dave's code.
Eric Anholt
Keith Packard
Keith Packard
Keith Packard
Keith Packard
Eric Anholt
Keith Packard
Eric Anholt