Commit Graph

68 Commits

Author SHA1 Message Date
Chris Wilson f2aafb9802 uxa: Silence compiler warning for const arguments
i965_video.c: In function 'gen6_create_cc_state':
i965_video.c:1374:12: warning: passing argument 4 of
'intel_bo_alloc_for_data' discards 'const' qualifier from pointer target
type [enabled by default]

Repeated ad nauseam.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-02-21 11:29:42 +00:00
Zhigang Gong 1e0d702c3a uxa/glamor/dri: Enable the pageflip support on glamor.
To support easy buffer exchange at glamor layer, glamor
added a new API glamor_egl_exchange_buffers() to exchange
two pixmaps' EGL image and fbos and textures without
recreating any of them. But this simple method's requirement
is that there are two pixmaps. A exceptional case is:
If we are using triple buffer when do page flipping, we
will have an extra back_buffer which doesn't have a pixmap
attached to it. Then each time we set that buffer to a
pixmap, we will have to call the create_egl_textured_pixmap
to create the corresponding EGL image and fbo and texture
for it. This is not efficient.

To fix this issue, this commit introduces a new back_pixmap
to intel structure to hold the back buffer and corresponding
glamor resources. Then we will just need to do the light
weight buffer exchanging at both DDX and glamor layer.

As the new back pixmap is similar to the screen pixmap
and need to be handled carefully when close screen. As the
glamor data structure is a per screen data, and will be
released at its close screen method. The glamor's close
screen method must cleanup the screen pixmap and back
pixmap's glamor resources. screen pixmap is easy to get,
but there is no good way to store the back pixmap.

So the glamor add a new API glamor_egl_create_textured_screen_ext
function to pass the back pixmap's pointer to glamor layer.

This commit make us depend on glamor commit: 4e58c4f.
And we increased the required glamor version from 0.3.0 to 0.3.1

Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-02-21 08:42:12 +00:00
Zhigang Gong ce7a57994d uxa/dri: Refine the pageflip processing.
Add a new element back_name to intel structure to track
the back bo's name then avoid flink every time.
And at function I830DRI2ExchangeBuffers, after finish
the BO exchange between info's front and back pixmap,
it set the new front bo to the screen pixmap. But the
screen pixmap should be the same as front's pixmap,
so this is a duplicate operation and can be removed.

Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
2012-02-21 08:40:10 +00:00
Chris Wilson 87bed52180 Include a local copy of list.h
In 1.11.903, the list.h was renamed to xorg-list.h with a corresponding
change to all structures. As we carried local fixes to list.h and
extended functionality, just create our own list.h with a bit of
handwaving to protect us for the brief existence of xorg/include/list.h.

Reported-by: Armin K <krejzi@email.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45938
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-02-11 21:02:22 +00:00
Chris Wilson 4db1bb3fd8 Removed deprecated xf86PciInfo.h includes
The driver should and does provide its own PCI-IDs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-01-08 17:34:48 +00:00
Chris Wilson b7f5d75aa5 Silence uxa-only compilation
Kill the stray warning for the undeclared extern used by the module
loader.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-18 16:25:28 +00:00
Chris Wilson a8fe50ab65 uxa: Explicitly check for libdrm_intel in configure
And remove the excess dependencies from the common files.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-17 21:26:34 +00:00
Chris Wilson 1128825efb uxa: Wakeup 3s after the last rendering to reap the bo-cache
libdrm expires its bo 2s after entry into the cache, but we need to free
a buffer to trigger the reaper. So schedule a timer event to trigger 3s
after the last rendering is submitted to free any resident bo during
long periods of idleness.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-13 11:27:17 +00:00
Chris Wilson 85d3dc5910 uxa: Reset size limits based on AGP size
The basis for the constraints are what we can map into the aperture for
direct writing with the CPU, so use the size of the mappable region as
opposed to the size of the total GTT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-12-02 10:22:51 +00:00
Zhigang Gong fbabe60f48 glamor: Initial commit to introduce glamor acceleration.
Added one configuration option --enable-glamor to control
whether use glamor. Added one new file intel_glamor.c to
wrap glamor egl API for intel driver's usage.
This commit doesn't really change the driver's control path.
It just adds necessary files for glamor and change some
configuration.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-11-17 01:10:21 +00:00
Chris Wilson 3771387ad1 Compile out UXA if so desired
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-11-16 22:15:39 +00:00
Chris Wilson edbeab8c4e sna: Reduce and clarify dependencies
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-11-16 22:15:39 +00:00
Chris Wilson 2174f84015 uxa: Remove caching of surface binding location
If the pixmap were to be used multiple times within a batch with
mulitple formats, the cache would only return the initial location with
the incorrect format and so cause rendering glitches. For instance, GTK+
uses the same pixmap as an xrgb source and as an argb mask in order to
premultiply and composite in a single pass. Rather than introduce an
overly complication caching (handle, format) mechanism, kiss and remove
the invalid implementation.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40926
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-11-03 20:41:31 +00:00
Chris Wilson 7c50205323 Remove vestigial includes from DRI1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-10-12 20:36:53 +01:00
Daniel Vetter d0184b5909 snb: implement PIPE_CONTROL workaround
Sandybdrige requires an elaborate dance to flush caches without
hanging the gpu. See public docs Vol2Part1 1.7.4.1 PIPE_CONTROL
or the corrensponding code in mesa/kernel.

This (together with the corresponding patch for the kernel) seems to
fix the hangs in cairo-perf-traces I'm seeing on my snb machine.

v2: Incorporate review from Chris Wilson. For paranoia keep all three
PIPE_CONTROL cmds in the same batchbuffer to avoid upsetting the gpu.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-10-11 09:54:17 +02:00
Chris Wilson 0a74cd77a3 video: check that the pixmap exists before use
Now, the pixmap being used is meant to the Screen pixmap and by rights
that has to exists in a GPU buffer! Evidence contrary to the above
exists and so we had better check that we have a bo before using...

Reported-by: Toralf Förster <toralf.foerster@gmx.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40439
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-08-29 10:41:26 +01:00
Kenneth Graunke e3a0960871 render: Refactor to use newly shared pipeline setup code in i965_3d.c.
Slightly generalize the shared SF and CC code to accomodate both.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28 15:01:03 -07:00
Kenneth Graunke 682a690bfe Xv: Refactor out pipeline setup functions for future reuse in render.
While we're at it, make the functions simply take an intel_screen_private
pointer directly instead of having to fetch it from ScrnInfoPtr.

Also coalesce some gen6/gen7 functions that were 98% identical.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-28 15:00:56 -07:00
Chris Wilson 7538be3315 dri: Enable triple-bufferred pageflips
By popular demand.

Triple-buffering trade-offs output latency versus jitter. By having a
pre-rendered frame ready to swap in following a pageflip, we avoid the
scenario where the latency between receiving the flip complete signal
from the kernel, waking up the vsynced application, it render the new
frame and then for the server to process the swap request is greater
than the frame interval, causing us to miss the vblank. The result is
that application can become frame-locked to 30fps. Instead, we report to
the application that the first frame swap is immediately completed,
supply a new back buffer (or else the rendering would be blocked on
waiting for the front-buffer to be swapped away from the scanout) and
let them proceed to render the second frame. The second frame is added
to the swap queue, and the client throttled to vrefresh. (If the client
missed the vblank, the swap queue is empty and the client is immediately
woken again, whilst the pageflip is pending.)

Note, for practical reasons this only applies to page-flipping, for
example, calls to glXSwapBuffer() on fullscreen applications.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-11 22:13:01 +01:00
Chris Wilson 2608a367ac dri: Prevent abuse of the Resource database
The Resource database is only designed to store a single value for a
particular type associated with an XID. Due to the asynchronous nature
of the vblank/flip requests, we would often associate multiple frame
events with a particular drawable/client. Upon freeing the resource, we
would not necessarily decouple the right value, leaving a stale pointer
behind. Later when the client disappeared, we would write through that
stale pointer upsetting valgrind and causing memory corruption. MDK.

Instead, we need to implement an extra layer for tracking multiple
frames within a single Resource.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=37700
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-07-11 21:46:36 +01:00
Chris Wilson 97e9557619 intel: Restore manual flush for old kernels
Daniel Vetter pointed out that the automagic flush by the kernel for the
busy-ioctl was only introduced upstream in 2.6.37. So we still need to
manually emit a flush on old kernels.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-08 13:38:48 +01:00
Chris Wilson 59ed6b05db Revert "i965: Convert to relative relocations for state"
This reverts commit d2106384be.

Breaks compiz (but not mutter/gnome-shell) on gen6. Not sure if this is
not seem deep interaction issue with multiple clients sharing the GPU or
just with compiz, but for now we have to revert and suffer the inane
performance hit. It looks suspiciously like another deferred damage
issue...

Bugzilla: 51a27e88b073cff229fff4362cb6ac22835c4044
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-07 16:16:58 +01:00
Chris Wilson ad22003033 i965: Avoid transform overheads for vertex emit where possible
Minor improvement as the bottlenecks lie elsewhere. But it was annoying me.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-07 15:09:21 +01:00
Chris Wilson 8dc99b305a i965: Reset vertex_id after every batch
So that we always remember to re-emit the initial vertex elements state.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 22:30:29 +01:00
Chris Wilson 6f104189bb Take advantage of the kernel flush for dirty bo in the busy ioctl
Rather than just creating and submitting a batch that simply contains a
flush in order to periodically ensure that rendering reaches the
scanout, we can simply ask the kernel whether the scanout is busy. The
kernel will then submit a flush on our behalf if it is dirty, which
takes advantage of the kernel's dirty state tracking.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 19:24:30 +01:00
Chris Wilson 314439860e Remove unused function 'intel_bo_alloc_for_data'
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 17:20:04 +01:00
Chris Wilson 79444291a3 i965: segregate each vertex element into its own buffer
Reduce the number of relocations emitted by only emitting one relocation
per vertex element per vertex buffer.

References: https://bugs.freedesktop.org/show_bug.cgi?id=35733
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 16:42:57 +01:00
Chris Wilson d2106384be i965: Convert to relative relocations for state
References: https://bugs.freedesktop.org/show_bug.cgi?id=35733
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-04-04 15:57:28 +01:00
Chris Wilson 630d77bf10 Add a DRI2SwapEventPtr typedef for retro xservers
Because people are still trying to build upon our solid historical
foundations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-30 07:25:57 +01:00
Keith Packard e1ff518230 Handle drawable/client destruction in pending swaps/flips
A pending swap or flip holds references to drawables and clients which
become invalid when destroyed. Add suitable resources to the database
to track those lifetimes and clean up the pending data structure then.

Later, when the pending swap or flip occurs, handle a missing drawable
by just discarding the flip or swap. Handle a missing client by not
sending an event or reply.

Signed-off-by: Keith Packard <keithp@keithp.com>
2011-03-23 17:14:12 -07:00
Keith Packard aa0328f342 dri2: Make DRI2FrameEvent public and use instead of void *
Instead of using void * for all of the flip_info and swap_info
pointers, just make the underlying structure a public data type and
use that.

Signed-off-by: Keith Packard <keithp@keithp.com>
2011-03-23 17:14:12 -07:00
Chris Wilson 049ce4397d Give each user of tiling separate xorg.conf options
So that you can indeed allocate a linear framebuffer if you so desire
without breaking mesa.

Adds:

Section "Driver"
  Option "LinearFramebuffer" "False|True" # default false
EndSection

to xorg.conf

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-09 08:37:02 +00:00
Chris Wilson 3e28a0c0b4 Create the UXA generational resources during screen create
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20 15:13:33 +00:00
Chris Wilson fd9235ebe0 Delete unused memory allocation flags.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-08 19:46:37 +00:00
Chris Wilson 03248a7984 Cache the fixed crtc<->pipe relationship
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-08 19:46:36 +00:00
Chris Wilson 00a2aee38d Remove unused I830Output
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-08 19:46:36 +00:00
Chris Wilson a851879695 Remove bitrotted, but fortunately unused, I830CrtcPrivate
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-08 19:46:36 +00:00
Chris Wilson 968151898b Remove unused GTT/Map sizes and addresses
These have been made obsolete by KMS and GEM.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-08 19:46:36 +00:00
Chris Wilson 19b5817a54 Remove unused struct _intel_memory definition
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-08 19:46:36 +00:00
Chris Wilson 53fbc9f176 Don't replace the scanout bo through PutImage
As the bo may be pinned for either use by the scanout or through sharing
with another application, under those circumstances we cannot replace
the bo itself but must force the blit for PutImage.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31367
Reported-and-tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-30 16:48:52 +00:00
Chris Wilson 875d482835 i830: amalgamate consecutive composites into a single primitive
Improve aa10text on i845 from 218kglyphs/s to 234kglyphs/s

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-23 19:42:19 +00:00
Mario Kleiner 2177e60321 Fix reporting of pageflip completion events on multi-head.
When a drawable is page-flipped on multiple crtc's (fullscreen
drawable on mirror-mode or multi-head x-screen), only one pageflip
event is finally delivered, after the last participating crtc signals
flip completion, this to avoid visual corruption.

Old code returned vblank count and timestamps of flip completion
of this last crtc, instead of the values of the "master crtc", the
one that was used for initially scheduling/triggering the pagflip
via vblank events. (master = I830DRI2DrawablePipe(drawable))

This patch makes sure that the pageflip completion values of the
"master" crtc are returned, otherwise client applications will
get confused by the random (msc, ust) values returned by whichever
crtc was the last to complete its flip. Without this, the returned
values change randomly and jump forward and backward in time and
count.

Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-16 11:42:43 +00:00
Chris Wilson f3a47d7f23 snb: Cache pixmap binding locations
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 14:21:06 +00:00
Chris Wilson 4d48fed9aa snb: Cache state between composite ops
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 14:21:06 +00:00
Chris Wilson 55c5f1876e Wait on the current buffer to complete when running synchronously.
And remove the vestigal wait upon changing crtc as this is more properly
done in the kernel.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson 3cc74044ce i965: Amalgamate surface binding tables
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson a1fa0dbfda i965: Upload an entire vbo in a single pwrite, rather than per-rectangle
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson 0bb135c40e Disable BLT for i830 and 845G
This pair of chipsets seem broken beyond repair, specifically the
erratum that causes the wrong PTE entry to be invalidated, so disable
our incorrect attempts to use the BLT on those devices.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 22:29:52 +00:00
Zou Nan hai 5bed685f76 add BLT ring support
gen6+ platform has a BLT engine with seperate
command streamer to support BLT commands.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[ickle: merge trivial conflict]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01 10:37:51 +00:00
Xiang, Haihao 3213849907 Xv: setup pipeline for Xv on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:51:13 +08:00