Commit Graph

2450 Commits

Author SHA1 Message Date
Shuang He 0a0731c11d Fix value for MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW
Since the change to scan-line based video sync, (rather than vblank-
based), we've only been getting tear-free video on one of the two
pipes. This fixes that bug by using the correct constant for waiting
on PIPEA.
2009-04-07 12:32:59 -07:00
Carl Worth 940c2aad4d Don't clip video to CRTC in the case of textured video
Since we're not limited by a single overlay plane on a single pipe,
we want to not clip at all, (so that the correct video appears on
both pipes).

This fixes bug #20980 which shows a video spanning two pipes
being rendered incorrectly.
2009-04-07 12:32:58 -07:00
Zhenyu Wang 63b4b5efac quirk LVDS on ibase MB890 855GM board
fix bug #19529
2009-04-07 10:55:35 +08:00
Carl Worth 5d9d9a2e46 Fix new video sync-to-blank code for multi-head
We need to account for a non-zero Y offset for the CRTC. Without
this, we don't sync to the correct region, so tearing becomes
visible again.
2009-04-06 14:02:08 -07:00
Carl Worth 3d4ee3cac1 Remove support for 'auto'(-1) value of XV_SYNC_TO_VBLANK
We previously had a heurstic here where we would only sync to vblank
for windows that covered more than 25% of the screen. We don't need
this anymore since the new approach to sync, (WAIT_FOR_SCANLINE_WINDOW),
is not excessively costly for small windows.
2009-04-06 11:31:20 -07:00
Carl Worth bc3312fd7c Use WAIT_FOR_SCAN_LINE instead of WAIT_FOR_VBLANK
Either way, the goal is tear-free video playing. But waiting for
a scan-line window not only has the advantage of being cheaper
for small windows, but also avoids hanging the GPU in the case
of the pipe getting turned off, (by screensaver, for example),
while a batch is waiting for a VBLANK that will never occur.

This fixes that GPU hang.
2009-04-06 11:16:53 -07:00
Jesse Barnes 6cd914ef31 Fix offset in begin_gtt_access case
Don't use bo->virtual in the begin_gtt_access case, use the framebuffer
mapping and bo offset instead.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-04-03 11:15:18 -07:00
Zhenyu Wang fad714c400 SDVO: fix output flag dumping for unknown type
Found by Hugo Jacques <hugo.jacques@verint.com>
2009-04-01 10:11:35 +08:00
Hugo Jacques 00de1757dd SDVO: add composite TV out support 2009-04-01 10:10:05 +08:00
Jesse Barnes 087f72e1f5 Match GTT unmap with map in KMS rotation case
Missed this when the GTT unmap call was added.  If we don't do this we
trigger an assertion in libdrm, since the buffer has never been mapped
normally.

Fixes bug #20943.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-03-31 07:51:35 -07:00
Zhenyu Wang 4f046af760 Disable LVDS detect methods
Both methods ACPI lid and SWF bit have issues in LVDS detect from
wider testing. Fallback to origin code.
2009-03-31 14:32:43 +08:00
Albert Damen e964d4e53a Non-GEM allocations incorrectly force TILE_NONE (bug 20797)
With -intel 2.6.3 performance was very bad when using a non gem enabled kernel
(2.6.27) and EXA. For example sauerbraten ran with 4 fps and screensaver GLBlur
with 1 fps. With -intel 2.6.1 performance was good using the same kernel.

Git bisecting led me to commit f1ed73c1ef3e3daa9f695194dcc813167cbcb53d (in 2.6
branch) "Make i830_allocate_memory take tiling parameters" as first bad commit.

Using gdb I found tiling was set exactly the same in 2.6.3 as in 2.6.1, so that
was good (TILE_XMAJOR for front, back and depth buffers).
Looking further I found the line mem->tiling = TILE_NONE; (line 961 in
src/i830_memory.c) at the end of i830_allocate_memory suspicious, as
mem->tiling now already gets set via i830_allocate_aperture and some buffers do
have tiling. Removing that line indeed fixed the performance issue. Now
sauerbraten runs with 30+ fps and GLBlur runs smoothly.
2009-03-30 11:38:02 -07:00
Jesse Barnes 51cf8a453c Require libdrm 2.4.6 for GTT unmap support
Need the new functions available.
2009-03-30 11:27:56 -07:00
Jesse Barnes 8dabcc4074 Tiling fixes, third set
Hopefully this concludes the fixes necessary to deal with the various
combinations of kernel and user level tiling.  We have several cases to
handle:
  1) KMS (kernel handles all tiling)
  2) UMS w/memory management + kexec fencing (kernel handles all tiling)
  3) UMS w/memory mangement but no kexec fencing (userland handles tiling)
  4) UMS w/o memory management (userland handles tiling)

For cases (1) & (2) we can use GTT mapping, which will give us good
performance and take care of allocating fence registers as needed.  It's
important *not* to have userland set up fence regs in this case, since
the kernel will be using all of them.

For case (3), we use the begin/end GTT map functions provided by libdrm,
in combination with pinning and fence register setup in i830_memory.c to
deal with tiled surfaces.  This also gives us good performance and
correctness.

For case (4) we use the old style virtual mapping + offset for dealing
with surfaces; note that UXA doesn't seem to work in this configuration
regardless of these fixes.

Fixes bug #20803.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-03-30 09:59:56 -07:00
Zhenyu Wang 375b2e40fc Disable LVDS config parsing from VBT for now
As wider tests showed that this doesn't work for all VBIOS, so
disable it for now and reenable it after we get reliable method.
2009-03-27 14:58:40 +08:00
Zhenyu Wang 69c84f2c82 gitignore intel_lid 2009-03-26 13:53:25 +08:00
Ma, Ling b5b3778064 disable center mode for 965GM and G4X platform
When disabling VGA mode, usually we don't need to touch VGA center mode.
However because of hardware reason, for Cresline, Cantiga & Eaglelake platform,
we have to disable center mode as well. The patch fixed bug- TV Out strobing regression,
reported by Robert Lowery in intel-gfx@lists.freedesktop.org mailing list.

Signed-off-by: Ma Ling <ling.ma@intel.com>
2009-03-25 15:27:25 +08:00
Zhenyu Wang e6af995b24 KMS: hook up output properties for randr
This gets output properties from kernel, then hook them up
for randr. So we can control output properties through randr
like in UMS.

Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2009-03-25 22:15:49 +08:00
Kalev Lember 74d0713e00 Fix VT switch with XV overlay video enabled.
drm_intel_bo_unpin() was called with NULL argument.

Signed-off-by: Kalev Lember <kalev@smartlink.ee>
2009-03-20 16:46:13 -07:00
Rémi Cardona b345b4e6ad clean up man page generation and remove all traces of the i810 driver
The i810 compatibility symlink has been broken since libpciaccess, so just
let it die.
2009-03-20 16:31:11 -07:00
Jesse Barnes 48b91e0668 Don't manage fences part two
Don't try to clear fences that were never installed.  Missed this bit in
the last fix for #20265.
2009-03-20 12:33:22 -07:00
Zhenyu Wang 28319d60aa Add a lid status test program "intel_lid" 2009-03-20 13:34:31 +08:00
Jesse Barnes 636d252f3b Don't install fences if the kernel is managing them
If execbuffer is setting up fences, it also means that the kernel is
managing them at pin time, so installing one in the 2D driver in that
case is an error.  The fence should stick around as long as the buffer
is pinned (the kernel won't steal these), though it will be freed at
leavevt and re-allocated at entervt.

On 965+ chips, the pin ioctl will *not* install a fence reg, but that's
also ok because all 965+ operations include tiling bits, and sw
fallbacks will be protected by prepare/finish access hooks, which will
either access the backing store or use the GTT, which will ensure proper
fencing at fault time.

Fixes #20265.

Acked-by: Eric Anholt <eric@anholt.net>
2009-03-19 13:25:29 -07:00
Carl Worth d92e6158c8 Revert the rest of the EXA_VERSION_MAJOR bump
This was mistakenly added in the unrelated change in revision
fe08b81d0f
and wasn't completely reverted in the later revision
78a60e1b66
2009-03-19 10:06:03 -07:00
Ma Ling 85e6b52858 Set SSC frequency for 8xx chips correctly
All 8xx class chips have the 66/48 split, not just 855.

Fixes #18358.
2009-03-19 09:10:19 -07:00
Jesse Barnes bedc894a56 Re-enable disabled outputs after rotation
The server may have made a DPMS call before doing rotation, so after we
do the mode set with the rotated framebuffer, we need to re-enable the
corresponding output(s).

Fixes bug #20573.
2009-03-18 20:19:44 -07:00
Jesse Barnes 6deb26ae7b Create known output configuration at EnterVT time
Since we added the pipe A force quirk (leaving pipe A on all the time),
DPMS calls to disable it have silently returned, leaving the pipe on.
If another driver (like vesafb) has enabled it, we may end up with a bad
configuration, leading to hangs or blank screens at VT switch time.

Fixes bug #19603.
2009-03-18 09:36:58 -07:00
Ma Ling 7c94227dd4 Use best PLL timing values for G4X platform
construct function to find precise parameters from internal spreadsheet
table on G4X platform.

Signed-off-by: Ma Ling <ling.ma@intel.com>
2009-03-17 10:41:38 +08:00
Ma Ling 48db5bde92 Define documented PLL timing limits for G4X platform
These timings on G4X platform were specified by internal spreadsheet from the chipset group.

Signed-off-by: Ma Ling <ling.ma@intel.com>
2009-03-17 10:41:02 +08:00
Keith Packard 78a60e1b66 Revert EXA_DRIVER_KNOWN_MAJOR bump
This was mistakenly added in the unrelated change in revision
fe08b81d0f
2009-03-16 08:41:52 -07:00
Zhenyu Wang 1a6e70cd98 TV: fix contrast and saturation for 945G
Bug #20670.
2009-03-16 15:42:50 +08:00
Zhenyu Wang 4e95327323 TV: force TV as connected with TV_Connector option
In order to bypass failure in TV load detect, TV_Connector option
will always force TV as connected with user specified connector type.
2009-03-16 15:15:26 +08:00
Eric Anholt d9dbdb3255 Add shave support, enabled by default.
This cuts down build system noise so that warnings are more visible.  The
old style output can be reenabled for build system debugging using
"make V=1", or --disable-shave at configure time.
2009-03-13 16:15:44 -07:00
Eric Anholt c3a82106a1 Move contributed m4 (dolt) to a subdirectory so we can include it with others. 2009-03-13 16:15:44 -07:00
Eric Anholt e0aba04da0 Add DCC register dumping. 2009-03-13 16:15:44 -07:00
Eric Anholt a57814cc13 Add dumping of 915 and 945 fence registers.
The debug dumper functions can now return NULL to indicate no output, so
we get appropriate results on 915, 945, and 965.
2009-03-13 16:15:44 -07:00
Eric Anholt 8166a7ff5c Add PGETBL_CTL to the debug output.
It's nice to know when it gets stomped on.
2009-03-13 16:15:44 -07:00
Keith Packard fe08b81d0f Use CopyArea to load glyphs from per-glyph pixmap to cache pixmap
With glyphs sitting in per-glyph pixmaps, there's no reason to use the CPU
to move them to the cache pixmap, and lots of reasons to use the accelerator.

Signed-off-by: Keith Packard <keithp@keithp.com>
2009-03-13 15:03:38 -07:00
Kalev Lember 2026c57cf0 Fix Xv crash with overlay video.
Bug #20585.
2009-03-13 16:01:43 -04:00
Jesse Barnes 3ef9d85371 Use UXA when KMS is active
EXA doesn't support KMS, so force UXA on if KMS is detected.  And warn
the user if they've specified something other than UXA in their
xorg.conf.

Fixes bug #20620.
2009-03-13 12:21:34 -07:00
Zhenyu Wang dc3ff0b514 Revert "SDVO: Switch control bus only before DDC access"
This reverts commit ddedf19f88.

After i2c STOP, control bus will return back to internal
registers. So this brings back to origin code that we switch
to DDC bus before START. But it's ideal to only issue DDC
bus switch after STOP, not before every START, which might eliminate
some complains from SDVO device, that will be another patch later.
2009-03-12 16:32:02 +08:00
Zhenyu Wang c6b0135d20 SDVO: reset privates before output setup
For multifunction encoder, forget to reset these values
will cause wrong output type in later mode setting
operations.
2009-03-12 16:31:01 +08:00
Dan Nicholson 28e7f0d71f Fix dist of xvmc sources
The XVMC AM_CONDITIONAL is only needed around the library expression.
None of the other definitons will cause anything to be built without
libXvMC, but they're needed for 'make dist'.

Signed-off-by: Dan Nicholson <dbn.lists@gmail.com>
2009-03-11 15:41:16 -07:00
Kristian Høgsberg 73db44e7ac Drop Legacy3D option, only use fixed texture space with non-gem.
With this change, we always expect the 3D driver to use GEM textures
when the 2D driver uses GEM.  When GEM is not available or disabled,
we fall back to legacy fixed textures.
2009-03-11 11:36:57 -04:00
Zhenyu Wang 2fcf4fcccf SDVO: fix pixel multiplier setting for TV
We should use preferred input timing's clock for correct
pixel multiplier setting, otherwise we might get inconsistent
multiplier setting on pipe and SDVO device for some modes.
2009-03-10 14:21:36 +08:00
Eric Anholt fb6e00f40f Fix XV with non-GEM kernels by allocating a larger fake bufmgr.
Ideally we'd not be using the EXA offscreen memory manager and just hand all
that memory to the fake bufmgr for non-GEM, but the fake bufmgr's too slow for
that, at least currently.  So compromise and take enough memory that it will
succeed at XV allocations but hopefully not anger tiny-aperture systems too
much.

Bug #20563.
2009-03-09 20:06:30 -07:00
Eric Anholt dc12c4b3eb Flip the update_dri_buffers test around to only run when DRI1 is active.
Fixes segfaults at startup with DRI2 and load detection, or with DRI disabled
entirely.
2009-03-09 12:51:29 -07:00
Xiang, Haihao 646e12a978 typo in intel.man 2009-03-09 10:59:36 +08:00
Eric Anholt 73aa23d915 DRI1: Update sarea (and other information) when CRTC configuration changes.
Bug #14423.

Signed-off-by: Eric Anholt <eric@anholt.net>
2009-03-06 14:49:31 -08:00
Eric Anholt abb213d933 Document the UXA AccelMethod.
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-03-06 14:34:24 -08:00