This adds back the resize hook so we can resize the front buffer under
kernel mode setting as well.
The patch also pulls the drmmode_* structs from drmmode_display.h into
drmmode_display.c and eliminates the header file.
Set alignments, tile settings and flags correctly in the 2D driver to support
tiled rendering. UXA's create pixmap function currently assumes the worst
about the alignment constraints; that should probably be fixed. Some of the
1M alignment fixes could probably be done more cleanly as well.
It never worked with any upstream linux kernel, and is quite heavily
deprecated. A new solution based around DRI2 will probably be
forthcoming. Pageflipping itself is next.
This eliminates the separate i830_allocate_memory_tiled function which means
that all memory objects will have tiling parameters set correctly.
Signed-off-by: Keith Packard <keithp@keithp.com>
This should be a noop. If it wasn't a noop, it means that on pre-g33 chipsets
we were spamming some data into a page of system memory because we used a
virtual instead of a physical address. It was also supposed to not work when
we submit it from a batchbuffer, as we have been doing for some time now.
This code has existed since about the beginning of the driver's existence,
with no justification.
My checks for DRM enabled were a bit too extensive; drmCommandWriteRead is
part of libdrm which the driver is always linked against. Only the symbols
in the DRI module need to be checked here.
Signed-off-by: Keith Packard <keithp@keithp.com>
GEM requires the DRI extension module currently, so make sure that is loaded
(by checking for the DRIQueryVersion symbol) before trying to call it. This
allows the server to start with the DRI extension disabled.
Signed-off-by: Keith Packard <keithp@keithp.com>
This eliminates the cost of EXA migration management while providing full
pixmap allocation control to the driver. The goal is to make something
useful for UMA drivers.
Update clock gating disable bits to match docs and allocate a power context
memory area so that newer chips can save state and power down the render unit.
GEM needs memory alignment requirements sent at pin time, which is a bit
after the allocation itself. Store the required alignment in the memory
object for later use by pin.
non-965 tiled frame buffers have fairly strict alignment requirements, 512K
on 8xx and 1MB on 9xx, plus they must be aligned to the size of the
allocation.
This reduces the CPU overhead of memcpying them in every time, for a speedup
in aa24text of around 30%. This is based on work by Carl Worth which is
in the intel-batchbuffer branch.
Kristian Høgsberg
Jesse Barnes
Eric Anholt
Owain G. Ainsworth
Keith Packard
Dave Airlie
Julien Cristau
Zhenyu Wang
Carl Worth
Jesse Barnes