Commit Graph

26 Commits

Author SHA1 Message Date
Keith Packard b2d058d80c Rename uxa using _ instead of caps 2008-08-05 15:41:52 -07:00
Keith Packard 12df8f40d2 Use dri_bo for all object allocations, including pixmaps under uxa 2008-08-05 15:40:14 -07:00
Eric Anholt ecf19e1cda Change most usage of pixmap offsets to using a reloc macro.
This is based on airlied's RING->BATCH commit.  The 965 code still needs to
be fixed up for relocations.
2008-06-10 11:37:03 -07:00
Zhenyu Wang 79fde3ad7a Check pitch for EXA operation
2D pitch limit applys to all chips. Pre-965 chip has
8KB pitch limit for 3D. 965 supports max pitch by current
exa (128KB).
(cherry picked from commit 8187a5a16f8bd8f0ba5e7f5357f355928b3b8f07)
2008-05-07 13:42:38 +08:00
Keith Packard 6459805964 Transformed coord computed using floats. Don't move bilinear composite dst.
The homogeneous coordinate computation in the core server cannot be used for
many legal matrices as it overflows. Just use floats in the driver; faster
and avoids troubles.

When compositing with bilinear filter, don't push the dst coordinates around
as that makes the output blurry when pixels are aligned.
2008-03-21 03:12:36 -07:00
Keith Packard 4b9b7b007d Handle projective transforms on 9xx for Composite.
Projective transforms require un-normalized texture coordinates and the use
of the texldp instruction. The coordinates are passed as x/y/z/w (the z is
unused, but there isn't a vertext format for just x/y/w).
2008-03-18 14:19:12 -07:00
Keith Packard 4f5500abe2 8xx/9xx can handle textures to 2kx2k. 965 can do 8kx8k 2008-03-18 14:10:25 -07:00
Eric Anholt 69fbc17441 Change OUT_RING and similar calls to OUT_BATCH for batchbuffer merge 2008-03-14 10:18:11 -07:00
Eric Anholt c20d78a7bc Add workarounds for 830/845's lack of a8/x8r8g8b8/x8b8g8r8 support.
When we have unset channels (color for a8, or alpha for x8*), force them
to the appropriate value in the texture combiner rather than relying on getting
the desired results from teture mapping.  Performance is the same on 865, so
multiple paths aren't necessary and we can use the less friendly texture
formats everywhere.
2008-03-13 15:25:13 -07:00
Eric Anholt 9a62d3b598 Remove i830+ driver's use of CARD*/INT* types for great justice.
Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
2008-03-11 12:07:52 -07:00
Kristian Høgsberg 9fd13e6773 Silence warnings about possible uninitialize use of dst_format.
Whoa, gcc got a lot smarter about warnings.  If iXXX_get_dest_format()
doesn't support the picture format passed in it won't initialize the
uint32_t pointed to by dst_format and return FALSE.

What gcc now can detect is if dst_format is used without checking the
return value, it might be used uninitialized.  This patch makes sure
we always check the return value before using dst_format.
2008-03-11 13:48:07 -04:00
Zhenyu Wang 5faee02e97 EXA: fix tiled dest rendering on i8XX chips 2007-10-10 13:55:30 +08:00
Eric Anholt ceb6dd7244 Fix context switching between DRI and X.
Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients.  This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
2007-06-12 10:04:39 -07:00
Wang Zhenyu 4120a20626 EXA: add render enter helper function
That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
2007-05-18 10:10:34 +08:00
Wang Zhenyu cebdb8bfc6 EXA: set enabling bits properly for i830
This was found when debug exa on a 865GV, we should set
pipeline state bits properly, otherwise the engine will hang.
2007-04-20 10:54:34 +08:00
Wang Zhenyu ab5bdee8a6 EXA: fix i830 render
Fix tex blend pipeline in case that src/mask pict has no
alpha. Unmask color buffer write disable bits. These make
rendercheck run fine on 855GM.
2007-04-17 16:23:46 +08:00
Wang Zhenyu 1a29750b8d EXA: fix 830/845G pict format
Fallback in 830/845G when pict format is a8, x8r8g8b8 or
x8b8g8r8. The hw doesn't support them.
2007-04-16 16:21:39 +08:00
Wang Zhenyu 3a634bbd19 EXA: Add i830 supported pict format XRGB8888, XBGR8888 2007-04-16 15:14:49 +08:00
Wang Zhenyu 3bcb9a0b4b EXA: i830 render misc fix and cleanups
Try to map texture stream when setup texture map, and use
correct order in load_immediate_1 cmd, which fixed crash on
845GV. Also remove some flush cmds.
2007-04-16 14:27:49 +08:00
Wang Zhenyu 6cd3b2c2de EXA: i830 fix blend action
i830_get_blend_cntl() has already added S8 offset.
2007-03-27 15:34:32 +08:00
Wang Zhenyu 35b3dd881a EXA: fix i830 componentAlpha support
Pick fix from i915 render, change tex blend pipeline for CA.
2007-03-27 15:33:43 +08:00
Wang Zhenyu df96d9a11d EXA: fix i830 texture setup
Use LOAD_IMM_2 helper cmd for tex setup. Enable RepeatNormal
support. Fix A8 format, i830 can support it now.
2007-03-27 15:32:53 +08:00
Eric Anholt 1623b47c48 Switch the RECTLIST vertex order to (x2, y2), (x1, y2), (x1, y1).
This is the documented correct ordering, and while the previous ordering
(reversed) worked on some hardware, it failed on others.

Reported by:	Wang Zhenyu <zhenyu.z.wang@intel.com>
2007-02-13 17:42:47 -08:00
Eric Anholt 681b91924c Add subpixel offsets to fix accelerated rotated rendering on i915.
This fixes the rendercheck "transformed src/mask coords 2" tests. Previously,
the source pixels chosen would be off by one in some cases.

The particular values were taken from Mesa, which uses .125 offsets (except
apparently broken for y), but the signs are changed.  I would be happier if
I had better justification for why this worked.
2007-02-02 17:41:40 -08:00
Eric Anholt 5238ff9c80 Naming and formatting cleanup in Render acceleration code. 2007-01-31 14:01:41 -08:00
Eric Anholt c47210d94e Move the render code to non-EXA-specific filenames. 2007-01-31 12:50:31 -08:00