dc18eaa585
sna: Make the failure to create render caches non-fatal
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-12 12:05:43 +01:00
b580abdfa6
intel: fix video xvPipe range check
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Pointed out by Russell King on irc.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-08-12 20:52:12 +10:00
44f848f9b2
sna: Fix typo in computation of texel offsets for tiled 8x8 blts
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Reported-by: Clemens Eisserer <linuxhippy@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53353
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 19:44:15 +01:00
b335d369bb
sna: Discard the GPU bo after syncing to CPU bo for writing
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 13:59:31 +01:00
029934662e
sna: Add a little DBG for promotion of CPU source bo
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
f20f8556bf
sna: Treat ShmPixmap as ordinary
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In theory the code handles the automatic promotion and demotion of the
GPU buffers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
16c751a06c
sna: Only mark userptr bo as snooped on non-LLC architectures
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
59359dba64
sna: Mark SHM userptr bo as unreusable
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
6448801050
sna/gen2-5: Substitute an equivalent BLT composite operation
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
f464d508c8
sna/gen6+: Try to use the BLT to avoid TLB misses
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
e9c0e54e69
sna: Handle userptr failures more gracefully
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-11 11:12:33 +01:00
5d6d9231cd
sna: Reset BLT state after copy-boxes
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-10 23:07:07 +01:00
50bfc172f1
sna: Improve a DBG statement
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-10 22:49:26 +01:00
b33f6754a9
sna: Add assertions to 8x8 tiled BLTs and reset BLT state afterwards
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Reported-by: Clemens Eisserer <linuxhippy@gmail.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=53353
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-10 22:01:23 +01:00
ff54d4af39
sna: Add a couple of debug options to control use of BLT patterns
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References: https://bugs.freedesktop.org/show_bug.cgi?id=53353
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-10 21:41:38 +01:00
2230614403
sna: Use the HAS_SEMAPHORES parameter when available
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 19:45:09 +01:00
465ae1840a
sna: Use a compile time constant for determine the zeroth bit
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 12:24:17 +01:00
85192f00e3
sna: Ignore trailing bits when comparing lines inside the bitmap
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References: https://bugs.freedesktop.org/show_bug.cgi?id=51422
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 12:18:48 +01:00
edc1427f3d
sna/gen5: Add DBG for context switching
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 10:53:40 +01:00
fec78ddc60
sna: Add DBG option to disable discarding of glyph masks
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 10:08:52 +01:00
b0cd430082
sna/gen5: Fix use of uninitialised rgba value for DBG
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 10:07:06 +01:00
9ad923f95c
sna: Minor DBG for fallback glyphs and discarding the mask
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-08 09:59:50 +01:00
1a0590d133
sna: Check the composite extents against the clip
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When computing the composite extents (as opposed to the composite
region) also check if the resultant box overlaps the destination clip
region (we know it already fits into the extents). This helps in cases
with small roi against clipped drawables, such as drawing text onto
expose events.
References: https://bugs.freedesktop.org/show_bug.cgi?id=51422
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-07 17:19:52 +01:00
5f5a10ef04
Add Haswell PCI IDs
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Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-07 11:35:19 +01:00
d8f7f933bc
sna: Format markup to suppress compiler warning
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-05 17:18:54 +01:00
4d0a259988
sna/gen6: Compile fix for DBG
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-05 11:03:40 +01:00
d917a276bf
sna/gen4: Restore the w/a flush for fill/copy as well
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So far, it looks like that the only one we can indeed drop is the
composite with mask.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 18:05:03 +01:00
d754bc3435
Fix build failure when passing --with-builderstring.
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If --with-builderstring="foo" is passed to configure (and sna enabled):
CC sna_driver.lo
src/sna/sna_driver.c: In function 'sna_init_scrn':
src/sna/sna_driver.c:1023:7: error: token ""foo"" is not valid in preprocessor expressions
Fix the missing defined() around the BUILDER_DESCRIPTION variable.
Signed-off-by: Cyril Brulebois <kibi@debian.org>
2012-08-04 16:35:58 +01:00
4bad76b451
sna/dri: Don't force ring selection if we have semaphores
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 14:32:04 +01:00
fb7b584ec9
sna/dri: Correct ring selection for a busy bo
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Confused the RENDER ring with the BLT, limiting swap performance.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 14:32:04 +01:00
20e58077fe
sna/gen6: Reduce ring switching for overlapping copy boxes
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 11:21:10 +01:00
2345227663
sna/gen7: Use a temporary to avoid switching rings for overlapping copies
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 11:12:12 +01:00
61ec2999af
sna/gen4: Restore w/a flush for video
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One flush removal too many, keep those fingers crossed that the others
do not make an unwanted return.
Reported-by: Roman Jarosz <kedgedev@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53119
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 10:34:49 +01:00
5833ef173a
2.20.3 release
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-04 09:32:35 +01:00
036b90f099
sna/gen7: Correct number of texture coordinates used for video
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Fixes regresion from
commit 33c028f8be
2012-08-03 21:42:28 +01:00
05dcc5f169
Pass the chipset info through driverPrivate rather than a global pointer
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 21:42:28 +01:00
2b3f4ca33a
Unexport intel_chipsets
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Only used by the core module code, so make it static.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 21:42:28 +01:00
5ff749727d
sna/gen7: Add constant variations and hookup a basic GT descriptor for Haswell
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 12:26:12 +01:00
cd028cad3d
sna: Limit the batch size on all gen7 variants
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Seems the limit on the surface state size is common across the family
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-03 12:21:46 +01:00
4cd9ec9d40
uxa: fix 3DSTATE_PS to fill in number of samples for Haswell
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The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen6_upload_invariant_states().
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:29 +01:00
412668464c
uxa: set "Shader Channel Select" fields in surface state for Haswell
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For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:26 +01:00
a47ba68996
uxa: fix max PS threads shift value for Haswell
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The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:23 +01:00
ce4421e175
uxa: use at least 64 URB entries for Haswell
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-03 12:20:18 +01:00
8c880aa34c
uxa: add IS_HSW() macro to distinguish Haswell from Ivybridge
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-08-03 12:11:59 +01:00
0c0d1d956a
Introduce a chipset identifier for Haswell (Ivybridge successor)
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Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2012-08-03 12:10:54 +01:00
146959dd5e
sna: Drop the clear flag as we discard the GPU damage
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Hopefully only to keep the sanity checks happy...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 23:44:05 +01:00
7404e3085b
sna: Ensure we only mark a clear for a fill on the GPU bo
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 23:39:13 +01:00
ca46d1c7a1
sna/gen7: Prefer the BLT for self-copies
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Looking at the test results for a third time, gives the edge to the BLT
again.
2012-08-01 20:21:45 +01:00
e4a3cd3d16
sna: Add validation of the clear flag to pixmap debugging
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 17:37:33 +01:00
eaeda34bef
sna: Fix computation of st values for SIMD8 dispatch
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Fixes regression with enabling 8-pixels.
Reported-by: Mehran Kholdi <semekh.dev@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53044
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2012-08-01 16:23:05 +01:00
Chris Wilson
Dave Airlie
Paulo Zanoni
Cyril Brulebois
Gwenole Beauchesne