Commit Graph

76 Commits

Author SHA1 Message Date
Xiang, Haihao 3213849907 Xv: setup pipeline for Xv on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:51:13 +08:00
Xiang, Haihao 73d4c7d7b8 Xv: set the surface state base address
To prepare for Xv on Sandybridge. It is easy to fill the binding
table without relocation and make sure that the pointer to binding
table only uses bits[15:0].

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:38:25 +08:00
Chris Wilson 4083197a44 Include a chipset generation number to clarify device specific paths.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-07 13:26:07 +01:00
Chris Wilson 5c663ce844 Rename common infrastructure to the intel namespace.
After splitting out the i810 driver into its own legacy directory, we
can identify the common routines not as i830 but as intel. This
clarifies the code which *is* i830 specific.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-25 13:18:01 +01:00
Chris Wilson 797d173a9a i810: Move into a legacy directory.
The driver is still built but is no longer under active development so
move it and supporting files to a new directory.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-25 13:18:01 +01:00
Chris Wilson c942585098 Emit the flush after a potential draw from the BlockHandler.
As the batch submit may not trigger further drawing through flushing the
vertices, pass the requirement to emit the flush down to the submission
routine so that the flush can be appended after the final commands.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-21 21:45:04 +01:00
Chris Wilson 8c1a8d2297 Revert "xp:trapezoids"
This reverts commit f429fb9d87.

An experimental patch I forgot was on my main branch as I was bugfixing.
ARGH!
2010-06-09 10:03:29 +01:00
Chris Wilson f429fb9d87 xp:trapezoids 2010-06-08 19:52:46 +01:00
Chris Wilson dcef703a7c Kill paranoid assertions on every write into the batchbuffer.
On my PineView box these represent ~5% overhead on x11perf text:

Before:
16000000 trep @   0.0020 msec (495000.0/sec): Char in 80-char aa line (Charter 10)
12000000 trep @   0.0022 msec (461000.0/sec): Char in 80-char rgb line (Charter 10)

After:
16000000 trep @   0.0020 msec (511000.0/sec): Char in 80-char aa line (Charter 10)
16000000 trep @   0.0021 msec (480000.0/sec): Char in 80-char rgb line (Charter 10)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-05-24 09:33:35 +01:00
Chris Wilson 5e04a81369 i830: Remove vestigal debugging ALWAYS_FLUSH and ALWAYS_SYNC
These are now debugging options exposed in Xorg.conf, and now unused int
the source code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-05-17 15:16:25 +01:00
Daniel Vetter bdf0ee509c i965 Xv: fix chroma pitch
In my recent fix for the chroma pitch for i915 xvmc I've forgotten about
i965 class hw. For videos with a non-even sized stride (measured in dwords)
the chroma pitch was internally incosistent and one dword off.

Fix this by using pitch2 for the chroma pitch in i965 textured video like
everywhere else.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27417
Tested-by: Nick Bowler <nbowler@draconx.ca>
Tested-by: Sven Arvidsson <sa@whiz.se>
2010-04-08 17:21:18 +02:00
Daniel Vetter 57c0043b9a Xv: fixup relocation in i965_video.c
The previous code made no sense, (multiplying an offset by 4 is
meaningless). It could have onlt worked with the offset being
fortuitously 0.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Carl Worth <cworth@cworth.org>
2010-03-04 09:38:38 -08:00
Daniel Vetter ce6526b9b4 Xv: kill unnecessary parameters for hw PutImage functions
This is the first part of my small crusade to rip out x1, x2, y1, y2
from I830PutImage*. These variables have strange semantics (they
change from simple integers to fixed-point values somewhere in
the middle) and don't really seem to be what we actually need.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-07 10:25:07 -08:00
Chris Wilson cd475bad23 batch: Ensure we send a MI_FLUSH in the block handler for TFP
This should restore the previous level of synchronisation between
textures and pixmaps, but *does not* guarantee that a texture will be
flushed before use. tfp should be fixed so that the ddx can submit the
batch if required to flush the pixmap.

A side-effect of this patch is to rename intel_batch_flush() to
intel_batch_submit() to reduce the confusion of executing a batch buffer
with that of emitting a MI_FLUSH.

Should fix the remaining rendering corruption involving tfp [inc compiz]:

  Bug 25431 [i915 bisected] piglit/texturing_tfp regressed
  http://bugs.freedesktop.org/show_bug.cgi?id=25431

  Bug 25481 Wrong cursor format and cursor blink rate with compiz enabled
  http://bugs.freedesktop.org/show_bug.cgi?id=25481

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2009-12-07 11:15:42 +00:00
Chris Wilson 98e1121036 Remove flush parameter from intel_batch_flush()
There is only a single caller that wishes to forcibly append a flush
into the batch: intel_sync(). So move the logic there.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2009-12-02 20:49:54 +00:00
Chris Wilson 57336c26f1 Rename I830Sync() to intel_sync()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2009-12-02 20:43:05 +00:00
Chris Wilson 67af5a9925 Check that batch buffers are atomic.
Since batch buffers are rarely emitted by themselves but as part of a
sequence of state and vertices, the whole sequence is emitted atomically.

Here we just enforce that batches are marked as being part of an atomic
sequence as appropriate.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2009-11-10 15:19:08 +00:00
Chris Wilson 3c0815abf2 conf: Add debugging flush options
Make the following options available via xorg.conf:
  Section "Driver"
    Option "DebugFlushBatches" "1" # Flush the batch buffer after every
                                   # single operation;

    Option "DebugFlushCaches" "1" # Include a MI_FLUSH at the end of every
                                  # batch buffer to force data to be
                                  # flushed out of cache and into memory
                                  # before the completion of the batch.

    Option "DebugWait" "1" # Wait for the completion of every batch buffer
                           # before continuing, i.e. perform synchronous
                           # rendering.
  EndSection

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2009-10-14 11:53:20 +01:00
Eric Anholt 7bbf4ac713 Rename the xv pPriv to adaptor_priv to reflect whose private it is. 2009-10-08 15:34:09 -07:00
Eric Anholt f309d47524 Call pPixmaps plain old pixmaps. 2009-10-08 15:34:09 -07:00
Eric Anholt af27a3a0a5 Rename the xf86 screen private from pScrn to scrn. 2009-10-08 15:34:09 -07:00
Eric Anholt cc5d3ba3c3 Rename the screen private from I830Ptr pI830 to intel_screen_private *intel.
This is the beginning of the campaign to remove some of the absurd use of
Hungarian in the driver.  Not that I don't like Hungarian, but I don't need
to know that pI830 is a pPointer.
2009-10-08 15:34:09 -07:00
Eric Anholt 8ae0e44e42 Move to kernel coding style.
We've talked about doing this since the start of the project, putting it off
until "some convenient time".  Just after removing a third of the driver seems
like a convenient time, when backporting's probably not happening much anyway.
2009-10-06 17:10:31 -07:00
Eric Anholt 33c488e836 Remove error state dumping code.
This is replaced by intel_gpu_dump, and would no longer be used once UMS is
gone.
2009-10-05 13:19:57 -07:00
Daniel Vetter 5ce944994d Xv: kill hw double buffering logic
The idea for the hw double buffering support is to program two fixed
buffers and then only switch buffers in the OCMD register. But the driver
as-is always programs the new buffer address (in both register sets
when double buffered). Therefore we gain nothing by using this hw
capability. Scrap the software support for it.

When double buffered, we now allocate just a buffer of size 2*size and
switch between the two parts purely in software.

To make reviewing this easier, I'll shortly explain the differences of how
double-buffering (i.e. tear-free video) is achieved before and after this
change:

- When double buffer, allocate a buffer twice the size (unchanged).
- Depending upon the currently shown buffer-half, copy the new frame into
  the other buffer-half. In the old code this is done by using the right
  set of buffer offsets, either *Buf0Offset or *Buf1Offset. The new code
  simply programs the offset for the right buffer-half into the single set
  of offsets. The end-result is unchanged.

Now the big difference in hw-programming:

Old: Programm new buffer offset into both sets of _hw_ buffer offset
registers. Depending upon the current _sw_ buffer, select the _hw_ buffer
and program this into the OCMD register. This just complicates matters
unnecessarly.

New: Just always use the hw buffer 0.

And then it's again the same story in both old and new code:

- Execute an overlay flip (MI_OVERLAY_FLIP) to read in the contents of the
  hw registers into the shadow hw registers (which are actually being used
  by the overlay, not the ones we write stuff into). This is synchronized
  with the respective crtc vblank by the hw.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-05 13:07:42 -07:00
Daniel Vetter 232418d72e Xv: use is_planar_fourcc helper some more
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-10-05 13:07:42 -07:00
Eric Anholt 222b52ef16 Align tiled pixmap height so we don't address beyond the end of our buffers. 2009-08-07 18:20:24 -07:00
Zhenyu Wang 150c9adebc Xv: fix domain usage for binding table on i965+ chips
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2009-06-30 11:12:12 +08:00
Zhenyu Wang 7770958e42 Add XV support on IGDNG
This brings necessary change for IGDNG for texture video support
from 2D render code.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2009-06-30 11:12:12 +08:00
Keith Packard 11a853bd8e Hold reference to video binding table until all rects are painted.
The optimization of unreferencing the binding table when the relocation is
posted causes the object to be dereferenced for each box in the clip list,
causing general chaos in the buffer manager. It's easier to just hold a
reference to the object until all of the boxes are painted and then drop it.

Signed-off-by: Keith Packard <keithp@keithp.com>
2009-05-01 11:55:13 -07:00
Keith Packard ed492131c1 3D_STATE_VERTEX_BUFFERS takes four 32-bit values, not three.
The spec says this command takes an extra (mbz) 32-bit value, so let's
provide it with one.

Signed-off-by: Keith Packard <keithp@keithp.com>
2009-05-01 11:54:48 -07:00
Keith Packard 66d1536a2e Don't bother to enable VF statistics during 965 video playback
This was used while bringing up the driver to debug vertext fetches.

Signed-off-by: Keith Packard <keithp@keithp.com>
2009-05-01 11:54:42 -07:00
Eric Anholt 393abc15b7 Now that video destination pixmaps are always in BOs, no more MarkSync. 2009-04-27 17:05:59 -07:00
Eric Anholt 73b7190421 intel: Nuke shared-entity support (zaphod mode).
It's been broken for years now, and KMS offers a much better chance of getting
this working sensibly without making a mess of the 2D driver.
2009-03-06 13:26:10 -08:00
Xiang, Haihao a625a07022 XvMC: fix broken xvmc on 965 2009-02-25 16:48:22 +08:00
Kristian Høgsberg 872aadc710 Make Xv used a buffer object instead of i830_memory.
We still pin the buffer object in case of overlay, but for textured video
we're now no longer using i830_memory for Xv anymore.
2009-02-18 17:26:06 -05:00
Eric Anholt a340fe5e42 Use intel_emit_reloc from video to prettify 965 render bind_bo setup. 2009-01-20 10:50:20 -08:00
Eric Anholt 946c7ef817 Do check_aperture_space and batch_start_atomic for i965 video.
This increases the overhead for video in the presence of cliprects, but we
were already doing nasty things in that case and don't seem to care.  This
could fix potential bad rendering or hangs with video, particularly with
DRI2.
2009-01-20 10:50:19 -08:00
Eric Anholt 7be668179a Move 965 video setup to a separate function so we can move it around. 2009-01-20 10:50:19 -08:00
Keith Packard 90b28a5655 Handle drm_bo_map failure in 965 video and composite paths.
These two paths allocate a number of objects directly.

Signed-off-by: Keith Packard <keithp@keithp.com>
2009-01-06 09:31:39 -08:00
Eric Anholt 48c113ade2 Emit proper relocations to pixmaps in BOs in i965 video. 2008-12-04 17:48:45 -08:00
Eric Anholt ae2cd8b75e Move i965 video surface state and binding table to BOs. 2008-12-04 17:48:45 -08:00
Eric Anholt 1b3c3c9d79 Move i965 video vertex data to BOs.
This eliminates extra syncing when clipping is involved.
2008-12-04 17:48:45 -08:00
Eric Anholt 8482597259 Move remaining i965 video programs to BOs. 2008-12-04 17:48:45 -08:00
Eric Anholt 40671132cb Move i965 video wm and sampler state to BOs. 2008-12-04 17:48:45 -08:00
Eric Anholt 48803eb746 Stop allocating unused scratch space for i965 video. 2008-12-04 17:48:45 -08:00
Eric Anholt f3fe46b557 Move i965 video vs/sf state to BOs. 2008-12-04 17:48:45 -08:00
Eric Anholt 4b9d3eac57 Move i965 video cc state to BOs. 2008-12-04 17:48:45 -08:00
Eric Anholt 176e92d89f Move I965DisplayVideoTextured unit state setup to separate functions. 2008-12-04 17:48:44 -08:00
Eric Anholt 61929f4c64 Move I965DisplayVideoTextured surface/sampler setup to separate functions. 2008-12-04 17:48:44 -08:00