For some reason, the code was preferring the last possible output when
mapping outputs to crtcs. Use the earlier CRTC instead to make the i830
driver consistent with BIOS usage.
Oops--looks like a typo to me; the code was callint set_target_output
instead of set_active_outputs.
BIOS loops waiting for the SDVO input to sync before enabling outputs, this
makes sense to me.
Instead of delaying pll/pipe/plane enables to the dpms function, turn them
on right away in the crtc_set_mode function. To avoid rewriting these
registers in the subsequent dpms function, check each register written there
to see if the enable bit is already on and don't rewrite.
Instead of growing virtual to fit our desired sizes, if it is set in the
config file, use the value as the virtual size and make the default
configuration fit within that size (if possible).
Pull xf86CrtcConfig out of the driver private structure and allocate a
ScrnInfo private index for it. Also, make the arrays of outputs and crtcs
dynamic instead of fixed.
We can't figure out which chips are supposed to have TV out, so instead we
prod the TV_DAC register to see if it will hold the value written to it, if
not, we assume the chip doesn't have TV out.
These names are reasonably short and describe the connector rather than the
target media, but we don't appear to have any way to determine what is on
the other end of the wire. More importantly, they're all unique now.
SDVO multiplier on 965 is in the dpll_md register; for some reason, that
needs to be written along with the dpll value or the multiplier doesn't get
set correctly.
xf86DDCMonitorSet dumps all of the DDC-discovered modes
into the monitor mode list without checking to see if they
are already present. This provides an ever-changing list of
modes for outputs which have no DDC and which simply duplicate the monitor
mode list.
I was having consistent system lockups when the vga restore
was first. Moving it to the end has reduced them to an infrequent
occurrence (but, alas, it has happened once since). This does not
make me happy.
DOUBLE_WIDE mode is needed when the pixel clock is > 90% of the core
clock rate. The code guesses what the core clock rate is based on
the bus (AGP -> 133MHz, PCI-E -> 200MHz).
Keith Packard
Keith Packard
Keith Packard
Eric Anholt
Keith Packard
Joshua J. Berry