This eliminates the cost of EXA migration management while providing full
pixmap allocation control to the driver. The goal is to make something
useful for UMA drivers.
The root window visual can not be changed. Neither at runtime nor
through the configuration file. The xserver simply selects the first one
that matches the class (usually TrueColor). I need a root window visual
with stencil buffer because my compiz plugin uses the it for some
operations. This patch reorders the visuals that the 3D driver reports
and puts the one with stencil (and depth) bits as first.
When page flipping is enabled, we need to make sure any changes to the front
buffer are reflected in the back buffer(s) or corruption might occur at page
flip time. So make the damage handler work on 965 by adding appropriate tiling
flags and pitch adjustments.
The EmitFlush in i830_dri.c was added as a pageflipping workaround, and was
noted to not even be sufficient then. There's no reason for it to be there,
so it's removed. After that, we just have to not emit an MI_FLUSH if we
already had, and cursor movement no longer bashes memory manager.
GEM needs memory alignment requirements sent at pin time, which is a bit
after the allocation itself. Store the required alignment in the memory
object for later use by pin.
Order hardware status page setup more reasonable after
all memory bound, in case new chipset requires non-stolen
page and that could be bound then.
Also clean up drm irq handler install function, and put
first install in starting stage later than status page setup,
so we won't make device cry for uninitialized status page.
Some of the hw state restoration callbacks may want to use the ring for various
things like stopping video playback, so leave the ring enabled until we get
back from RestoreHWState. Also rename the functions so that their purpose is
clearer and remove a couple of redundant lines.
This really isn't an error in general. If vblank pipe setup really fails for
some reason, it'll be obvious enough when the user tries to use vblank events
for something.
Patch from Hong Liu.
While this has been a desired feature for some time, to allow for reallocation
of the front buffer, it was made more necessary by the desire to avoid
requiring a NO_MOVE buffer type in TTM because buffer objects may not be left
pinned over VT switch. This is a step towards making those buffers
movable and resizable.
We want to associate plane A with pipe B on pre-965 mobile chips, since that's
the only way to get framebuffer compression on the builtin LVDS on those
platforms. However, if we do this swapping and DRM isn't aware of it, we may
end up requesting vblank events for the wrong pipe, or setting up SAREA buffer
swap state incorrectly.
This mod checks whether DRM supports the new plane->pipe swapping behavior, and
only enables the swapping if so. This should fix the bugs Lukas found and
debugged. Reviewed by Michel Danzer.
Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
If not available, AIGLX init will fail. While here, simplify DRIINFO tests
since we refuse to init with a version queried less than the version we
compiled against, anyway.
This is a step towards being able to expose buffer objects through the screen
private to DRI clients, instead of having them have to use the fake buffer
object type.
This fails in two ways. First, the kernel memory manager is not currently
suitable for doing the physical allocations we need, so we still use AGP for
those. Additionally, the DRI lock can't be initialized early enough for us, so
these buffer object allocations fail. This will be fixed by improving the
DRM interface.
Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
Eric Anholt
Jesse Barnes
Keith Packard
Jesse Barnes
Tomas Carnecky
Carl Worth
Dave Airlie
Matthias Hopf
Paulo Cesar Pereira de Andrade
Zhenyu Wang
Jesse Barnes
Jesse Barnes
Keith Packard
Michel Dänzer
Dave Airlie
Keith Packard