Commit Graph

3008 Commits

Author SHA1 Message Date
Chris Wilson 9b967807c2 Revert "i965: The RenderCache flush after every glyph is required for compiz"
This reverts commit 03e8351179.

* sigh.

This was only meant to be a temporary debugging hack, not for public
consumption (or embarrassment).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 20:47:17 +00:00
Chris Wilson 27e33928f8 i965: Mark sure we mark reused render targets as dirty
... or else we may forget to flush them again.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 20:43:22 +00:00
Chris Wilson 03e8351179 i965: The RenderCache flush after every glyph is required for compiz
... now who can explain why.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 19:27:57 +00:00
Chris Wilson d90c8f4d0b i965: Invalidate pixmap binding location on reuse.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 19:22:30 +00:00
Chris Wilson 4a186a6123 Always flush the batch before blocking for new X requests
This should prevent any lag when waiting upon user input, for example
whilst logging in with gdm.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 16:56:57 +00:00
Chris Wilson 00c204a7b2 snb: Only emit CC and DepthStencil bos once per batch
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 16:34:52 +00:00
Chris Wilson 084ae43110 snb: Restore drawrect, we need the implicit flush
Something is wrong, we should be tracking when to invalidate the caches
as appropriate, yet I can not finding the missing flush to replace the
implicit one of DRAW_RECTANGLE.

Fixes cacomposite.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 15:59:29 +00:00
Chris Wilson f3a47d7f23 snb: Cache pixmap binding locations
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 14:21:06 +00:00
Chris Wilson 4d48fed9aa snb: Cache state between composite ops
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 14:21:06 +00:00
Chris Wilson a58e5a1bdf snb: Emit more invariants only once
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-06 14:21:05 +00:00
Chris Wilson e8f41c3710 uxa: Prevent reading past the last byte on upload/download
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29752
Reported-by: Sergey Samokhin <prikrutil@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 22:36:21 +00:00
Matthias Hopf c2fac6ca10 Don't use hardware acceleration on Sandybridge rev 07 hardware or earlier.
This is known to lock up the GPU even with the workaround in place.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31773
Signed-off-by: Matthias Hopf <mhopf@suse.de>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 11:42:33 +00:00
Chris Wilson 8abade8a21 display: Flush any pending batches before changing modes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 09:57:52 +00:00
Chris Wilson 8450aba6c7 i965: Also flush the vertex buffer when restarting the array.
As a corollary to filling one vertex array and beginning a new one is
remembering to emit the old one before overwriting...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 01:08:51 +00:00
Chris Wilson f40f8bcf07 i965: Check for potential vertex array overflow every time
There was a reason why we need to check at the start of every composite
operation to see if we have enough space in the array to fit the
vertices, which I promptly forgot when moving the code around to make
it look pretty.

* sigh.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:28:11 +00:00
Chris Wilson 55c5f1876e Wait on the current buffer to complete when running synchronously.
And remove the vestigal wait upon changing crtc as this is more properly
done in the kernel.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson 3cc74044ce i965: Amalgamate surface binding tables
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson a1fa0dbfda i965: Upload an entire vbo in a single pwrite, rather than per-rectangle
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 14:05:30 +00:00
Chris Wilson 23437fe676 i965: Use reciprocal scale factors to avoid the divide per-vertex-element
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-03 01:16:16 +00:00
Chris Wilson 0bb135c40e Disable BLT for i830 and 845G
This pair of chipsets seem broken beyond repair, specifically the
erratum that causes the wrong PTE entry to be invalidated, so disable
our incorrect attempts to use the BLT on those devices.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 22:29:52 +00:00
Keith Packard 33c08882c0 Mark outputs as DPMSModeOn and restore backlight at mode set
The kernel always turns monitors on when doing mode setting, and so no
further DPMS action is required. Note this in the mode setting code by
marking the updated DPMS mode and restoring any saved backlight level.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2010-11-17 16:40:47 +08:00
Chris Wilson cc930a3761 uxa: Relax fencing some more for gen3
Allow fenced allocations even for small pixmaps if the kernel supports
relaxing fencing (where only the used pages are allocated).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-14 19:47:00 +00:00
Chris Wilson 3c5b1399e2 i915: Disable maximum state addresses
As the kernel controls the relocation of state buffers, we should not
hard code the maximum permissible value for them.

Fixes an eventual hang with full-gtt.

Reported-by: Peter Clifton <pcjc2@cam.ac.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-09 20:20:06 +00:00
Chris Wilson a44a63d2ff Wait for any pending rendering before switching modes.
A perennial problem we have is the accursed WAIT_FOR_EVENT hangs, which
occur when we switch the framebuffer before the WAIT_FOR_EVENT completes
and upsets the GPU.

We have tried more subtle approaches to detected these and fix them up in
the kernel, to no avail. What we need to do is to delay the framebuffer
flip until the WAIT completes, which is quite tricky in the kernel
without new ioctls and round-trips. Instead, apply the big hammer from
userspace and synchronise all rendering before changing the framebuffer.
I expect this not to cause noticeable latency on switching modes (far
less than the actual modeswitch) and should stop these hangs once and
for all.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31401 (...)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-05 10:07:46 +00:00
Chris Wilson 52b32436b9 Downgrade tiling allocation failure to a warning
We emitted this message as an error even though we fallback and attempt
to allocate a non-tiled framebuffer before failing (with an appropriate
error message).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-03 19:46:11 +00:00
Chris Wilson 18839aaec5 Fallback to shadow for Sandybridge if we don't have access to the BLT
If we attempt to emit BLT batches without kernel support, we just end up
with EINVAL and no rendering. Prevent this, and avoid uncached
rendering, by restoring the shadow fallback paths if there is no BLT
support.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-03 18:17:17 +00:00
Eric Anholt 8ff37667bf Remove the intermittent GEM_THROTTLE call.
This is a holdover from early GEM work when we weren't syncing on the
DRI client side.  It would keep clients from getting too far ahead and
killing their interactivity, by bringing everyone to a halt when
anyone was too far ahead.

Now, GL clients throttle themselves to avoid the problem, and it turns
out that in the case that they don't (long rendering to buffers with
no swap), this actually reduces X Server interactivity: instead of
lagging of X rendering behind input, you get no response for seconds
at a time, then a burst of rendering, then nothing again.

Reported by ajax.  Tested with moving a window while running
cairo-perf-trace on the GL backend (improvement) and X backend (no
significant change in responsiveness).
2010-11-02 10:58:46 -07:00
Xiang, Haihao 540c574218 render: use headerless render target write
It is weird that some rendercheck cases only work fine with headerless write.
Need to update intel-gen4asm to support headerless write

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-02 14:28:55 +08:00
Xiang, Haihao 7a3109312e render: acceleration for composite on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-02 14:28:55 +08:00
Xiang, Haihao 0ab2c05a29 render: fragments for composite on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-02 14:28:55 +08:00
Xiang, Haihao 21c86548dc render: fix send instruction used in sampling fragments
To prepare for composite on Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-02 14:28:55 +08:00
Xiang, Haihao 8d008ca89d render: set the surface state base address
It is the same as commit 73d4c7d7

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-02 14:28:55 +08:00
Chris Wilson b5ae596a07 Flush BLT batches before starting an atomic RENDER batch
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01 11:13:03 +00:00
Zou Nan hai 42363134bd Support BLT acceleration on gen6
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01 10:38:37 +00:00
Zou Nan hai 5bed685f76 add BLT ring support
gen6+ platform has a BLT engine with seperate
command streamer to support BLT commands.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[ickle: merge trivial conflict]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01 10:37:51 +00:00
Xiang, Haihao 6ec3ff134b Xv: don't call intel_wait_for_scanline on Sandybridge
MI_LOAD_SCAN_LINE_INCL command is not available on sandybridge.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:51:55 +08:00
Xiang, Haihao 9e73cbd7ee Xv: enable TextureAdaptor for Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:51:51 +08:00
Xiang, Haihao 3213849907 Xv: setup pipeline for Xv on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:51:13 +08:00
Xiang, Haihao 9e4dd27aa8 Xv: fragments for xv on Sandybridge.
Need to update intel-gen4asm to build these fragments

Signed--off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:46:14 +08:00
Xiang, Haihao e34b3f6ef5 Xv: Send instruction doesn't use implied move when sampling YUV surface
The two fragments will be reused for sampling YUV surface
and send doesn't have implied move on Sandybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:45:51 +08:00
Xiang, Haihao 73d4c7d7b8 Xv: set the surface state base address
To prepare for Xv on Sandybridge. It is easy to fill the binding
table without relocation and make sure that the pointer to binding
table only uses bits[15:0].

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2010-11-01 08:38:25 +08:00
Chris Wilson 5afc7472b1 intel: don't pass a dangling pointer to GET_PARAM
I fail at cut'n'paste.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29 12:25:23 +01:00
Chris Wilson 6b3ce2e870 uxa: Enable reduced fence sizes for i915
Depends on libdrm 362457715faacd3101929e5f0d8ae250d0ad09df (for
HAS_RELAXED_FENCING define).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29 11:07:50 +01:00
Adam Jackson b066ddda31 intel: Listen for hotplug uevents (V3)
This connects the kernel uevent indicating monitor hotplugging to the
RandR notification events so that X applications can be notified
automatically when monitors are connected or disconnected.

This also adds a configuration option to disable hotplug events.

V2: missed a #ifdef HAVE_UDEV around some udev-specific declarations

V3: document Hotplug option in man page

Signed-off-by: Keith Packard <keithp@keithp.com>
2010-10-22 08:35:29 -07:00
Eric Anholt a1c54f6964 Fix violation of gen6 requirements for depthbuffer tiling.
In general, demoting of tiling of DRI2 buffers seems dubious, as we've
got various bits of functionality that won't all work together unless
buffers are tiled as expected.  This just covers one instance of the
problem, caught by assertions in Mesa.

Fixes:
fbo-1d
fbo-d24s8.
glean/readPixSanity
glean/rgbTriStrip
glean/scissor
2010-10-18 14:39:25 -07:00
Chris Wilson 33133a1d38 display: do not report failure for setting unrecognised properties
We need to accept any changes to properties not handled by ourselves -- we
can't validate the changes ourselves. Denying those changes breaks EDID
reporting, for example.

Reported-by: Elvis Pranskevichus <el@prans.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-17 09:24:22 +01:00
Chris Wilson 8507ef50ba Fix driverName regression for i830 from 4083197a
Reported-by: Stefan Glasenhardt <stefan@glasen-hardt.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30808
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-13 09:51:57 +01:00
Chris Wilson 15aab1ef98 Move EDID_COMPLETE_RAWDATA define to intel.h to avoid redifinition warning
The compiler was simply warning that we defined the name prior to
including the original definition, so reorder.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-13 09:51:57 +01:00
Stefan Dirsch d2bc2212f8 Make driver compile for 1.6 Xserver series again. Part deux.
Signed-off-by: Matthias Hopf <mhopf@suse.de>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-12 12:30:41 +02:00
Chris Wilson 5472359d68 dri: Check for pixmap privates before dereferencing them
It is still possible for the pixmap allocator to return a software only
pixmap (i.e. without an associated GEM buffer or intel_pixmap), so check
before dereferencing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30707
Reported-by: Matthias Hopf <mhopf@suse.de>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 15:23:13 +01:00