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205 Commits

Author SHA1 Message Date
Eric Anholt aefa6fdfc5 Clean up GRF allocation (which was wrong at 16-register boundaries). 
Also use PS_MAX_THREADS rather than hard-coding 1 thread, and remove the dead
SF_KERNEL_NUM_URB macro.
 2006-08-02 21:14:14 -07:00
Eric Anholt 7a64e14624 Crank down the SF allocation and comment on why this is a fine lower limit. 2006-08-02 20:48:13 -07:00
Eric Anholt bc6a2bb757 Remove the clip URB allocation. 
Previously, the VS was misconfigured and exceeding its allocation, which the
(unused) clip was providing padding for.
 2006-08-02 20:34:57 -07:00
Eric Anholt defe279542 Correct the VS setup, and allocate a correct, minimal number of URB entries. 
The VS number of URB entries and URB entry size are always used, even when
the VS is disabled.  Similarly, the cache enable bit is always used.
 2006-08-02 20:32:41 -07:00
Eric Anholt b57ccb682c Replace the SF max threads setting with a define for easier tweaking. 
Tweak it to 1 for now.
 2006-08-02 19:46:15 -07:00
Eric Anholt 82037a1275 Remove CS URB allocation since we don't use any constants. 2006-08-02 19:33:28 -07:00
Eric Anholt 1d45668d7a We only need 3 vertices to fit in the URB, since we only dispatch 3. 2006-08-02 19:18:20 -07:00
Eric Anholt a076d35bed No GS URB allocation is necessary when the function is disabled. 2006-08-02 19:16:03 -07:00
Eric Anholt befa655168 Reduce URB_VS_ENTRY_SIZE to 1 as our vertices are under 8 floats. 2006-08-02 19:11:38 -07:00
Eric Anholt 33acbdca0a Remove the VS kernel and binding table. 
The VS URB entries have to remain as they're used to store the VF output which
isn't modified by a VS program.
 2006-08-02 19:09:19 -07:00
Eric Anholt aafa48cb85 Fix wm prog to correct the ordering of the Cr and Cb channels. 2006-08-02 18:26:26 -07:00
Eric Anholt bc2c842d93 Allocate space for the 965's state at the end of the video buffer. 
Fixes corruption in the first few lines of the video.

Based on 1b506798d98d911be733543da2c40cb451a28912
 2006-08-02 18:10:01 -07:00
Eric Anholt 524460ea1f Updated WM kernel to load video and do colorspace conversion. 2006-08-02 17:47:55 -07:00
Eric Anholt ba896c779c Updated grf/urb state for WM. 2006-08-02 17:47:37 -07:00
Eric Anholt 21b62df7c3 Move the WM kernel to a separate file. 2006-08-02 17:36:49 -07:00
Eric Anholt 5d3424492f Replace SF kernel with the one from broadwater-video HEAD. 2006-08-02 17:34:12 -07:00
Keith his master's voice Packard 3f158fd610 Nice texture coordinate gradient, broken slightly in y 2006-05-29 18:05:57 -07:00
Keith his master's voice Packard bb0ad04d46 Ok, finally something sensible up on the screen. 
Replace PS kernel with constant data source (pink).
Dodge g0/g1 so URB data doesn't land on top of thread data.
Flip source/dest coordinates (dunno why they're fetched this way).
 2006-05-28 22:59:58 -07:00
Keith his master's voice Packard ddf3e5b273 Using tiny rectangle, still locks up in pixel shader program somehow 2006-05-28 21:03:39 -07:00
Keith his master's voice Packard 2e16c79dc2 Lots more debug code. Appears to execute pixel shader thread now though. hurray! 2006-05-28 20:31:23 -07:00
Keith his master's voice Packard 79a514412b dump out piles of debug. Create VS thread just to see how it works 2006-05-28 16:09:59 -07:00
Keith his master's voice Packard 9c111d89fe Push all of the obvious Mesa state setting into the video code 2006-05-27 19:52:13 -07:00
Keith his master's voice Packard 01101196b1 flesh out cc state. set cull mode to none. enable sf kernel 2006-05-27 01:05:09 -07:00
Keith his master's voice Packard 462a860af8 Rename BRW instructions, check video instruction generation. Doesnt lock up, but doesnt display anything either 2006-05-27 00:17:25 -07:00
Keith his master's voice Packard 9ec7cf22e3 Use broadwater video code on broadwater hardware. Pad ring to even length. compute state base as address rather than offset 2006-05-26 21:30:55 -07:00
Keith his master's voice Packard f5fe700b9a Prepare real SF kernel and fake WM kernel 2006-05-26 13:47:39 -07:00
Keith his master's voice Packard 1549accb6f Scale video source vertices. Allocate space for kernels 2006-05-25 16:10:31 -07:00
Eric Anholt bce209cd3f Put in code for idling accelerator on subsequent cliprects. 2006-05-19 17:13:37 -07:00
Eric Anholt 3640117bd9 Set up the state buffer in framebuffer. 2006-05-19 17:10:04 -07:00
Eric Anholt de06cd70a9 Checkpoint for filling out more 3D state. 2006-05-18 18:27:11 -07:00
Eric Anholt ad7ec6a24b Checkpoint of BW textured video work, filling out vertex submission stuff and 
some more other state.
 2006-05-18 15:26:28 -07:00
Eric Anholt 291770efc6 Start laying out some of the bits that need to be done for BW textured video. 
Headers taken from TG code drop.
 2006-05-18 10:43:07 -07:00
Eric Anholt bc51d6525a Turn off overlay video on BW until we have stable PCI IDs so we can know whether 
the hardware supports overlay.
 2006-05-17 13:42:51 -07:00
Eric Anholt b0ac5303f3 Merge branch 'textured-video' into broadwater-video 
Conflicts:

	src/i830_video.c
 2006-05-16 15:21:17 -07:00
Eric Anholt c2cd10e1fb Flag the 3D state as dirty when we draw textured video, which should help 
rotation (I have other issues with rotation anyway).
 2006-05-16 10:10:33 -07:00
Eric Anholt 63a72e46fa Turn debugging back off. 2006-05-16 10:10:33 -07:00
Eric Anholt 01c043de03 Use linear min/mag blending. 2006-05-16 10:10:32 -07:00
Eric Anholt db3683907d For textured video, disable double buffering and sync before uploading new video 
data.  Allows more videos to play simultaneously.
 2006-05-16 10:10:32 -07:00
Eric Anholt 29a8e88ed0 Relax the alignment requirements for textured video. 2006-05-16 10:10:32 -07:00
Eric Anholt c9be11459b Enable overlay and/or textured video at runtime according to hardware 
capabilities.  Sets up 16 textured-video ports.  Left in one hack (disconnected
but advertised BRIGHTNESS and CONTRAST atoms) which may actually not be
necessary.
 2006-05-16 10:10:32 -07:00
Eric Anholt f268979a0c Correct drawing issues with planar formats when top or left != 0, and Y didn't 
get its offset.
 2006-05-16 10:10:32 -07:00
Eric Anholt b09fd42d70 Fix the planar formats to display correctly in textured mode. Still has issues 
with clipping, and some sampling differences between ximagesink and xvimagesink.
 2006-05-16 10:10:31 -07:00
Eric Anholt dd48790f46 Divide width by 2 in planar-to-packed conversion loop, since each pass through 
the loop writes two source pixels.
 2006-05-16 10:10:31 -07:00
Eric Anholt eec5e996ec Merge textured-video-wip to textured-video-planar-full. 2006-05-16 10:10:31 -07:00
Eric Anholt 4154a2f748 Experimental work to use a full pixel shader for planar to YUV conversion, which 
also doesn't quite work.
 2006-05-16 10:09:26 -07:00
Eric Anholt 3e0a9c9082 Do a separate BEGIN/ADVANCE_LP_RING set in the planar vs packed blocks, so I 
can adjust the planar code more easily.
 2006-05-16 10:09:26 -07:00
Eric Anholt 3af4a967e7 Add a couple of macros to simplify writing of video pixel shaders. 2006-05-16 10:09:26 -07:00
Eric Anholt 06e62ec521 Commit a WIP implementation of the planar video shader that does the 
planar-to-packed conversion for us.  Unfortunately the documentation is unclear,
and I haven't managed to get any implementation of it working correctly.
 2006-05-16 10:09:26 -07:00
Eric Anholt b1090a42b2 More magic number reduction in rotation code. 2006-05-16 10:09:26 -07:00
Eric Anholt 3a2d8af214 Add initial textured XV support for i915, which can do YUY2 and UYVY, but fails 
on I420 and YV12 currently, doesn't support the composite extension, and should
break XV support on non-i915.
 2006-05-16 10:09:25 -07:00